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DM365 MMC/SD0 SDIO0 Interrupts

Panchatcharam MURUGESAN
Prodigy 60 points

All,

    I have DM365 EVM and want to interface a SDIO card with it (The card shall be conencted to MMC/sD0 slot). MMC/SD portion of DM365 supports interrupts such as Read/write/respone CRC error, data timeout and response time out interrupts, SDIO card interrupt and Read wait interrupt.  As per SDIO user manual (found in TI website) ARM interrupt 26 (INT26) is associated with MMC/SD0 functions and ARM interrupt 23 (INT23) is associated with SDIO0 functions.
    My questions are as below
        1. Whether do we need to define two ISRs (one for handling MMC/SD0 interrupts such as Read/write/respone CRC error, data timeout and response time out interrupts, another one for SDIO0 interrupts such as SDIO card interrupt and Read wait interrupt)
       2. Is disabling any of the interrupt will affect the other?

      Please calrify it.......
 
Thanks,

Panch

  • 0
    TI__Expert 5475 points

    Hi,

    Will look into your question and will supply you with more answers in the following days.

    The MMC/SD peripheral seems to have 2 interrupt events and each event would require its own interrupt handler. I do expect to see independent interrupt control bits at both periheral and CPU interrupt handler levels. Will confirm on this in the following days too.

    Best regards, Zegeye

  • 0 in reply to Zegeye Alemu
    Prodigy 60 points

    Hi Zegeye,

          Thank you for your reply and desperately awaiting for your confirmation.

    Regards,

    Panch

  • 0 in reply to Panchatcharam MURUGESAN
    TI__Expert 5475 points

    Hi Panch,

    Yes, it is correct that  you would require 2 interrupt handlers. Each MMC/SD peripheral is have 2 dedicated interrupts. As you mentioned MMC/SD-0 has Interruts Numbers 23 (SDIO-0) and 26 (MMC/SD-0) allocated for it. Same for MMC/SD-1 where Interrupt Numbers 31 (SDIO-1) and 27 (MMC/SD-1) allocated for it.

    Each have dedicated interrupt control registers (enable/disable)-SDIOEN and interrupt flag registers (status)-SDIOST registers to control interrupt at the core level. At the CPU Level, the corresponding interrupt number fields mentioned above within the INTC module are used based on your interrupt mapping (IRQ or FIQ).

    Best regards, Zegeye

  • 0 in reply to Zegeye Alemu
    Prodigy 60 points

    Hi Zegeye,

                   Thank you for your timely reply. This helps us for now......

    Thanks,

    Panch