Hello,
My customer has DDR3 memory read/write error, one bit of write data is differrent when read.
We are checking the PCB layout rule, software leveling and so on now.
One thing we got is that DDR_CK/CK# is connected to GND through 0.1 uF Capacitor, not to VDDS_DDR.
They says that the wave form is clear and AC/DC timing is OK, but is that connection acceptable for AM335x and DDR3 ?
Regards,
Takeshi Matsuzaki
