• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 748 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2H14: Termination requirement for DDR3

Madhu Sharma
Expert 2915 points

Part Number: 66AK2H14

Hi,

When only one DDR3 IC is used per DDR controller ( One in DDR3A and other in DDR3B), Please let me know

Whether termination for address and control signals ( pull up to 0.75V) is necessary.

Thanks & Regards,

Madhu

  • 0
    TI__Guru**** 161600 points
    Hi,

    The schematic checklist (processors.wiki.ti.com/.../Keystone_Multicore_Device_Family_Schematic_Checklist is clear about that:

    - Address, command, clock signals must be routed in fly by topology with VTT termination. Balanced T routing is not supported on DDR3 design for these devices.
    - It is recommended to use dedicated ZQ resistor of 240 ohms 1% to be connected to each SDRAM ZQ pin (cannot share pins).
    - Each respective address and command net should be end terminated using a resistor (in the range of 39Ω to 49Ω) and connected to VTT. The preferred resistor value is 39Ω, 1%.
    - The clock nets shall be terminated with a series 39Ω, 1% resistor to a 0.1uF capacitor to DVDD15 (VDDq).
    - Each trace to the respective termination should be ≤ within 500 mils and the opposite side of the termination resistor should tie directly to the VTT rail.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 2915 points
    Hi Yordan,

    Thanks for the reply.

    The schematics checklist mentions the condition when more than one ICs are connected to a DDR3 controller. Since I am connecting only one IC, there will not be any T or fly-by requirement.
    For some other processors, if only one IC is connected to a DDR3 controller, termination is not necessary for address & control lines.

    Regards,
    madhu
  • 0 in reply to Madhu Sharma
    TI__Guru**** 161600 points
    Hi Madhu,

    It is still better to have termination on the DDR lines.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 46460 points

    Madhu,

    The response from Yordan is correct.  Even with a single SDRAM attached, we require use fly-by topology with VTT termination after the SDRAM per the stated routing guidelines.

    Tom