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About cache setting of DM642

jun wang53031
Prodigy 130 points

Hi,

              I used the evmDM642 to do some tests of video,I have some questions about the DM642 cache setting. In the reverse.pjt project provided by TI,there are have some

statements that I can't understand,I list in the below:

                CACHE_setL2Mode(CACHE_256KCACHE);      
                CACHE_enableCaching(CACHE_EMIFA_CE00);
                CACHE_enableCaching(CACHE_EMIFA_CE01);

             My question is:    CACHE_setL2Mode(CACHE_256KCACHE);   this statement means that all of the space of DM642 L2 is setting the cache,but

             #pragma DATA_SECTION(nMemTemp, ".INTPROCBUFF");
             #pragma DATA_ALIGN(nMemTemp,128);

             the nMemTemp is allocated to L2, In this case ,the L2 is used as SRAM,As we known,the L2 has been set to CACHE.

             I check the address of nMemTemp,it is allocate in 0x0000000,in the L2.

             So Why this memory is set to cache that can be use as a ram?

            Another question:

            CACHE_enableCaching(CACHE_EMIFA_CE00);
             CACHE_enableCaching(CACHE_EMIFA_CE01);

             That means keep the sapce of CE0 cacheable in L2? Or,cache the sapce of CE0 and CE1?

              Thank you very much!

    

              

 

  • 0
    TI__Mastermind 41665 points

    jun wang said:
    So Why this memory is set to cache that can be use as a ram?

    This sounds like it may be a bug in the project, allocating code/data to internal memory that is set to cache is a bad idea, with the CACHE_256KCACHE setting you no longer have any L2 memory internally. However it is ok to use the internal memory before it is configured as cache, or if it is configured as SRAM again later, for example the EMIF boot mode copies a 1k boot loader into 0x00000000 of L2 SRAM, but this memory can later be configured to cache after the boot loading is complete.

    I am not familiar with the reverse.pjt, where did you get it from? Note that DM642 is one of the older parts we offer, so it is unlikely that the software will be updated even if a bug is found.

    jun wang said:

                CACHE_enableCaching(CACHE_EMIFA_CE00);
                 CACHE_enableCaching(CACHE_EMIFA_CE01);

                 That means keep the sapce of CE0 cacheable in L2? Or,cache the sapce of CE0 and CE1?

    This means that the CE0 and CE1 spaces are now cacheable, so when you make accesses to CE0 and CE1 it will pass through the cache, meaning both a potential performance improvement for repeated accesses, and a potential concern of cache coherency depending on your system.