66ak2h14: HyperLink Boot ROM Segment Mapping

Jack,

Here is the update segment map for Keystone II devices.

As indicated in the ARM Bootloader user guide :

www.ti.com/.../spruhj3.pdf

"After configuration of the peripheral, the ARM core executes a WFI instruction that causes the ARM to suspend execution waiting for an interrupt. While the ARM is suspended, the HyperLink host can write the boot image into the MSMC. After the image is written, the HyperLink host must write the execution starting address of the image to the host boot data address register. The HyperLink host must interrupt the ARM to break out of the suspended state. Each time an interrupt is triggered, the ARM core will poll the host boot data address register to check if the boot image is ready. If the host boot data address register indicates the boot image is ready, the bootloader will begin executing the boot image at the address specified in the register"

You can refer to the SRIO example that we provide in the SDK to see how data gets pushed on the slave peripheral and then core0 wakeup takes place.

The srioboot_example is the host side code.

Regards,

Rahul

Rahul,

Thank you for your timely response. I will give this is try and let you know how it works out.

Regards, 

jack

Hi Rahul,

I'm using CCS7 with PDK_K2HK_4_0_4. There is no "examples/srio" folder. In fact, there is no "examples" folder at all. There are only three subdirectories under "<PDK_ROOT>packages/ti/boot" which are "post", "sbl" and "writer". I have also downloaded the "keystone2_boot_examples.zip" and it doesn't have any SRIO boot examples either. The link that you sent is not for the KeyStone II family so I assume this is the disconnect. Are you suggesting that I download the C66x PDK to look at the SRIO boot examples?

In my setup I'm not using any ARM cores. I'm using DSP CorePak0 on one EVMK2Hx board to load a boot image via HyperLink to a secondary EVMK2Hx board that has been configured to boot DSP CorePak0 via HyperLink. Hence, the instructions that you provided for bringing the ARM out of reset don't apply. However, I assume that the steps are similar looking at the DSP Bootloader Users Guide (sprugy5c.pdf). On the DSP side CorePak0 executes an IDLE instruction until an interrupt is received.

If you could provide the SRIO boot example code for the KeyStone II that would be helpful.

Thanks,

jack

Jack,

I am sorry, I meant there is an SRIO boot example in the Keystone I Processor SDK that you can use as reference.

I have attached the zip version of the SRIO folder so that you don`t have to install the SDK for the Keystone I devices as well.

7115.srio.zip

Unfortunately, we don`t have any support for slave boot modes like Ethernet , SRIO or Hyperlink  in the Processor SDK for K2H devices.

Here is some old Hyperlink boot test code that I found that you may be able to use as reference:

vusrLoopBoot.zip

Hope this helps.

Regards,

Rahul

Thanks for the information, I'll take a look at the code and let you know how it works out. 

Regards, 

jack

Hello Rahul, 

I'm still not having any luck accessing the remote devices MSM (0x0C000000) via HyperLink. Below are some observations:

(1) The HyperLink remote registers are not visible via offset (0x80) from the host HyperLink interface. I assumed that this was due to some configuration with the HyperLink interface in boot mode on the remote device. This is not the case when I have both boards running the example HyperLink demo application (hyplnk_K2HC66DevLibBiosExampleProject). 

(2) I'm not sure if I'm running in to issues with the PrivID or SecID settings. In the example code that works the PrivID is set to 12 on both Tx and Rx sides. I've read in the HyperLink Training Slides (Eindhoven_Jan_12-08_Intro_To_Hyperlink.pdf) that the "agreed" values from HyperLink Privilege index is 13 for request from a core and 14 for requests initiated from another master. Does this still hold for the KeyStone II part and should I be setting the PrivID to 14 to interface with the remote device? Are there any particular settings that need to be observed for the security bits?

(3) Based on the table that you supplied with the default segment mapping I have computed the following Tx side start addresses:

WIth the above memory map I attempted to perform a transfer to MSM of the device configured in HyperLink boot mode as follows:

uint32_t *hyplnk_RemoteMSMAddr_ptr = (uint32_t*)0x42400000;

*hyplnk_RemoteMSMAddr_ptr = 0xCAFEBABE;

The above transfer does not complete. No write occurs on the target DSP. Prior to the above setup I am configuring the HyperLink interface and setting the TxAddrOvly as follows:

TXAddrOvly.txSecOvl = 0;

TXAddrOvly.txPrivIDOvl = 14;

TXAddrOvly.txIgnMask = 5;

I've attempted a couple of different txPrivIDOvl settings with no luck. 

As a sanity check I did confirm that I can write to MSM on the Rx device from within the debugger. So the question is, what should the TXAddrOvly settings be to match up with a device configured to boot via HyperLink over DSP 0?

(4) It's not clear from documentation how to configure the HyperLink Boot device for a reference clock of 312.5 MHz. Bits 15:14 of the device configuration relate to the HyperLink reference clock. However, the only supported options, according to the latest KeyStone II reference manual, are 0 for 125 MHz and 1 for 156.25 MHz. The EVMK2Hx board clearly has a 312.5 MHz reference clock. What should the setting be for the reference clock in the boot configuration settings that I'm programming in the BMC for the device that is being configured for HyperLink boot via DSP0? Is 2 a valid option for the 312.5 MHz reference clock?

Any thought/suggestions would be appreciated.