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AM5728: RSTOUTn assertion every 50ms

Chad
Prodigy 190 points

Part Number: AM5728

I have a custom PCB which I have bringing up over the past few days, the PMIC and other circuitry are up and running, but I am seeing that the AM5728 asserting a low RSTOUTN signal every 50ms. The setup currently does not have a boot media to boot from (PCB bring-up first). I have read through the TRM extensively and of the global reset sources I suspect it could be from the MPU watchdog timer. The problem is I have not found documentation that firmly indicates this timing.

Any information is appreciated, thanks.

  • 0
    TI__Guru**** 393215 points
    Please see this note: processors.wiki.ti.com/.../AM572x_GP_EVM_Hardware_Setup However the timing is quite different from what you report. Does your custom board schematic follow the AM572x GP EVM schematic, especially for PMIC and reset connections?
  • 0 in reply to Biser Gatchev-XID
    Prodigy 190 points
    Hi Biser,

    Thank you for the reply. I am aware of the 7 second PMIC reset, this does not seem to be the issue. I am using a slightly different power on structure than the EVM schematic, (PMIC BOOT1 = 1 to use POWERHOLD toggle ON/OFF state) but power supplies are all connected the same as used with the EVM. The PORz is very similar and the signal has been verified to be acting correctly, however on my system RTC_PORZ and RTC_ISO are floating as the internal RTC is not used and to save routing congestion.

    I have compared many of the Power, Reset and Clocking related signals between our custom implementation and the EVM, the only differences noticed are those listed above.

    Thanks.
  • 0 in reply to Chad
    Prodigy 190 points
    I have found the source of this reset being issued. I have the strapping for the AM5728 configured in production mode, which as noted on page 7827 in the TRM, after 10 failed boots will issue a reset. I have changed to another strapping configuration (Recovery/Upgrade or Development Booting) and this causes the SOC to go up for 30 seconds and then I see the continual 50ms reset signals. For now I will hold off further testing until our boot image is ready to validate there is no other issues.

    Hope this can be helpful to someone.