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AM5728: PCIe register settings for de-emphasis and swing

matusan
Guru 10235 points
Part Number: AM5728

Hello, TI Experts,

 

Our customer sent us a question about PCIE.

They would like to know the De-EMPHASIS and SWING setting by reading the register with PROCESSOR-SDK-RTOS .

 

Question:

  Which register should we read to understand the De-EMPHASIS and SWING setting?

  Could you tell us the proper register address for PCIE_SS1?

    - De-EMPHASIS:                

    - SWING:

 

We would also appreciate if you tell us the bit description of those registers.

 

Best regards,

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points

    Hi,

    I looked through AM5728 TRM, only thing I found is: Table 24-904. PCIECTRL_PL_WIDTH_SPEED_CTL, Physical Address 0x5100 080C for PCIE SS1.

    BIT 20 CFG_UP_SEL_DEEMPH Used to set the de-emphasis level for Upstream Ports RW 0x0
    BIT 18 CFG_PHY_TXSWING Config PHY Tx Swing RW 0x0

    Given each field is just one-bit, I am looking for more info what can be configured and will update you.

    Regards, Eric

  • 0 in reply to lding
    Guru 10235 points

    Hi,

     

    Thank you very much for your kindness.

    I really appreciate your help.

    We are waiting for your update including "each bit field detail description".

    Best regards,

  • 0 in reply to matusan
    Guru 10235 points
    Hi,

    Thank you for your help.
    Do you have any update?

    Now, our customer is waiting for the answer too long.

    I would appreciate if you tell us about the progress on this.
    We are waiting for your update including "each bit field detail description".

    Best regards,
  • 0 in reply to matusan
    TI__Guru* 95265 points
    Hi,

    Sorry, I am still looking for this from HW team.

    Regards, Eric
  • 0 in reply to matusan
    Genius 3380 points
    Matusan, we asked a similar question many months ago and was told that the PCIe HW is 3rd party Intellectual Property and register settings are not disclosed. I believe what we seek is controlled by the function PlatformPCIESS2PhyConfig() from the sample code. Those registers are not listed at all in the TRM.
  • 0 in reply to Christopher Peters
    Guru 10235 points

    Hi,

    Thank you very much for your kindness.
    I really appreciate your help.

    We understand what you mean.
    We told the customer the DK-san's comment "Modifying them is not supported" as E2E thread below.
    e2e.ti.com/.../2114674

    So they understood "it is difficult to get the PCIE register description from TI for modifying registers."

    They just want to know "current De-emphasis configuration is -6bB or -3.5dB" for analyzing their system trouble by using AM5728.

    They just want to read the AM5728 registers and just want to know what is going on their system.

    Their AM5728 custom board system has serious trouble for long time. (detail is in the below E2E-thread)
    e2e.ti.com/.../608073

    So, any clue is helpful.
    For example, we found related description in the document as below;

    www.ti.com/.../sprugs6d.pdf
    Table 3-169 Link Control Register 2
    Current De-emphasis level
    0 = -6 dB
    1 = -3.5 dB

    Is it same for "BIT 20 CFG_UP_SEL_DEEMPH" of AM5728 PCIE register as Eric-san said?
    Like this information is also helpful.

    Best regards,

  • 0 in reply to matusan
    TI__Guru* 95265 points
    Hi,

    The Table 3-169 Link Control Register 2 of www.ti.com/.../sprugs6d.pdf
    Current De-emphasis level
    0 = -6 dB
    1 = -3.5 dB

    This is from Keystone I/II PCIE.

    The same register is Table 24-999. PCIECTRL_EP_DBICS2_LNK_CAS_2 for the AM5728 TRM. The address is 0x510010a0 or 0x518010a0.

    6 SEL_DEEMP Selectable De-emphasize R 0x0 =========> This bit is read-only.

    Sorry I don't have additional info for the: Table 24-904. PCIECTRL_PL_WIDTH_SPEED_CTL, Physical Address 0x5100 080C for PCIE SS1. As mentioned by DK, PCIe HW is 3rd party Intellectual Property and register settings are not disclosed.

    Regards, Eric
  • 0 in reply to lding
    Guru 10235 points

    Hi,

     

    Thank you very much for your kindness.

    I really appreciate your help.

     

    We understand " No additional info for the: Table 24-904. PCIECTRL_PL_WIDTH_SPEED_CTL" as you said.

    We would like to confirm one thing.

     

    We can identify "the current De-emphasis level is -6 dB or -3.5 dB"

    by reading the register bit value of PCIECTRL_EP_DBICS2_LNK_CAS_2.DEEMPH_LEVEL.

      - If this bit shows "1",  current De-emphasis level is -3.5 dB.

     

    Is this understanding correct?

     

    Best regards,

  • 0 in reply to matusan
    TI__Guru* 95265 points
    Yes, correct.
  • 0 in reply to lding
    Guru 10235 points

    Hi,

     

    Thank you very much for your kindness.

    I really appreciate your help.

    I will send the answer to the customer.

     

    Best regards,