RTOS/AM5716: Question about IO Pad Slew Control

Markus Mueller

Part Number: AM5716
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

I'm actually trying to manually configure the pin mux setting for some peripherals on the idkAM5718.
For this I watched at the code within the BOARD_init() function, especially Board_pinmuxConfig().

There some IO pads are configured with Slewcontrol = SLOW.

In the TRM (SPRUHZ7E , page 4121) I found this note:

===============================================
The default SLEWCONTROL settings in each pad configuration register must be used to
guarantee timings, unless specific instructions otherwise are given in the individual timing
sub-sections of the device Data Manual. The only exception is when the MUXMODE is
configured to select a vout*_* signal. In this case the corresponding SLEWCONTROL bit
must be configured to slow slew instead of the default fast slew.
===============================================

The Data manual (SPRS957D) does not say anything about setting the slew rate except for
vout*_* signals.
The pads that are configured as "SLOW" by Board_pinmuxConfig() are *not* from these types.
So why does Board_pinmuxConfig() configure SLOW slew rate while the TRM and data manual
specify to use default ("FAST") slew rate ?

I'm using PDK V1.0.6 and SYSBIOS 6.46.04.53

Regards,
Markus

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

The factory team have been notified. They will respond here.

0 Markus Mueller over 8 years ago in reply to Biser Gatchev-XID

Expert 1370 points

Hi

This is a reminder to not forget my post...

Regards,
Markus

0 Biser Gatchev-XID over 8 years ago in reply to Markus Mueller

TI__Guru**** 393215 points

Sorry about the delay. I have escalated the request.

0 melissaw over 8 years ago in reply to Biser Gatchev-XID

TI__Genius 15970 points

Hi Markus,

Can you give a few examples of the pins in question?

Please note that the default SLEW settings are shown in the CTRL_CORE_PAD_* register definitions in section 18.5 (Control Module Register Manual) of the AM571x TRM. The default slew settings are a mixture of fast and slow slew, depending on the pin. Also, the TI PinMux tool provides a graphically interface for configuring pin mux settings, and this tool automatically accounts for default slew settings.

Regards,

Melissa

0 Markus Mueller over 8 years ago in reply to melissaw

Expert 1370 points

Hi Melissa

See this TI example:

C:\ti\pdk_am57xx_1_0_6\packages\ti\drv\spi\test\src\am571x\SPI_idkAM571x_board.c

There is the function "MCSPI_Board_crossbarInit()" where the core pad regisers are configured as follows:

/* SPI3_SCLK */
HW_WR_REG32((SOC_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_MCASP4_ACLKX),
(CTRL_CORE_PAD_MCASP4_ACLKX_PUPDD_RX_MODE));

/* SPI3_D1 */
HW_WR_REG32((SOC_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_MCASP4_FSX),
(CTRL_CORE_PAD_MCASP4_FSX_PUPDD_RX_MODE));

With the symbols defined like this:

#define CTRL_CORE_PAD_MCASP4_ACLKX_PUPDD_RX_MODE 0xc0002 //(0x00040003U)
#define CTRL_CORE_PAD_MCASP4_FSX_PUPDD_RX_MODE 0xc0002 //(0x00040003U)

This sets the Bit 0x00080000 (Slew Control) to "1" which is "slow".
The reset default value for this bit is "0" (according to TRM; SPRUHZ7E chapter 18.5.2.2).
In the data manual I could not find a hint which would require to set these pins to a different value than default.
In contrast the data manual (SPRS957D, chapter 7.3.1.2) says:

=========================================
The default SLEWCONTROL settings in each pad configuration register must be used to guaranteed
timings, unless specific instructions otherwise are given in the individual timing sub-sections of the
datasheet.
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
=========================================

Regards,
Markus

0 melissaw over 8 years ago in reply to Markus Mueller

TI__Genius 15970 points

Markus,

Thanks for the example. I am looking into this. However, it may be a day or two until I have an answer.

Regards,

Melissa

0 Rahul Prabhu over 8 years ago in reply to Markus Mueller

TI__Guru** 116830 points

Markus,

The slew setting for those 2 pins appears to be a bug in that example code. The code was meant to override the setting from automated values generated from Pin Mux tool as the default board library sets this pin to MCASP transmit clock and frame clock previously. this was subsequently fixed in the board library when we integrated the output of pinmux tools into the board library so if you look at the file boardPadDelayInit.c file in the idkAM571x board library the pins are set to the mode 2 with the correct slew settings using

/* SPI3 - spi3_sclk on C18 - MySPI3 */
{0x1734, 0x10002, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* SPI3 - spi3_cs0 on D17 - MySPI3 */
{0x1740, 0x20002, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* SPI3 - spi3_d1 on A21 - MySPI3 */
{0x1738, 0x50002, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

but the INPUTENABLE setting may still be required so change the following macros to fix the issue.

#define CTRL_CORE_PAD_MCASP4_ACLKX_PUPDD_RX_MODE    0x40002 //(0x00040003U)
#define CTRL_CORE_PAD_MCASP4_FSX_PUPDD_RX_MODE      0x40002 //(0x00040003U)

Hope this helps

Regards,

Rahul

0 Markus Mueller over 8 years ago in reply to Rahul Prabhu

Expert 1370 points

Hi Rahul

Thank you for confirming that this is a bug.

Regards,
Markus

Processors

Processors forum

RTOS/AM5716: Question about IO Pad Slew Control