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Videoport and NDK

Victor Ivanov
Expert 1160 points

Hi all!

I work with DM648 installed on Evaluation Module.

I use Videoport 2 to get raw data from FPGA and Ethernet to send data to PC. I don't use any drivers to work with Videoport and I use Evaluation Version of NDK to work with Ethernet.

Until I added NDK to my application, videoport worked fine. However, after I had included NDK, I found out that videodata became incorrect.

It seems that not all data were copied from Videoport FIFO to my buffer.  I filled buffer with a pattern and then, after I got data from Videoport I checked the buffer and found several blocks of my pattern were not overwritten. Position and amount of these blocks seems to be more or less random.

I removed all my code which works with sockets and left only NDK initialization, but it didn't help. When I removed NDK initialization everything got fine.

It seems, there is an interference between Videoport and NDK. In NDK configuration I found only Interrupt number and I use different Interrupt numbers for NDK and my code.

What could be the reason of my problem?

Victor

  • 0
    Expert 1160 points

    Hi!

    I still try to understand the reason for my problem but I don't have any ideas.   :-(   As I understand from NDK documentation, it doesn't use EDMA (am I right?) so there shouldn't be any interference...

    It is enough to call      NC_SystemOpen( NC_PRIORITY_LOW, NC_OPMODE_INTERRUPT)    to cause corruption of Videodata. Not each frame is corrupted. 20-50 frames could be OK and then about the same amount of frames could be corrupted and again OK...

    Any ideas???

  • 0
    Expert 1160 points

    Hi again!

    I continued an investigation of my problem using the ideas provided by TI support and found out that the reason is not an interference  between my code which works with Videoport and NDK. Presence of NDK initialization (NC_SystemOpen) only causes more frequent data distortion and makes the problem easier to notice.

    As I understand now, the problem is caused by configuration (tcf file) which I took from helloWorld example from NDK. In tcf file there are the following lines:

    // Setup the L2 Cache and MAR bits
    bios.GBL.C64PLUSL2CFG = "64k";
    bios.GBL.C64PLUSMAR224to255 = 0x0000ffff;

    When I remove them, Videoport works fine. However, according to NDK documentation, NDK suppose presence of cache so I can't remove them permanently. Moreover, I tried how NDK works without them (just for experiment) and it worked about 10 times slower then with these lines.

    My code which works with Videoport based on the example, provided by Lyrtech. I made many changes because I work with 16 bits raw data while example works with some kind of video but in general my code does the same things.

    Any ideas...

    Victor

  • 0 in reply to Victor Ivanov
    Expert 1160 points


    it seems that my problem is related only to EDMA3 controller. I did the following test:

        static volatile Uint8 Src[BUF_LEN];
        static volatile Uint8 Dst[BUF_LEN];

        int i;
        for(i=0;i<BUF_LEN;i++)
        {
            Src[i]=i%256;
        }
        memset((void*)Dst, 0, BUF_LEN);

        EDMA3Regs = (CSL_Edma3ccRegs*)CSL_EDMA3CC_0_REGS;

        EDMA3Regs->DCHMAP[32]=0;
        EDMA3Regs->PARAMSET[0].OPT=0x00100008;
        EDMA3Regs->PARAMSET[0].SRC=(Uint32)&Src[0];
        EDMA3Regs->PARAMSET[0].A_B_CNT=0x0001<<16|BUF_LEN;
        EDMA3Regs->PARAMSET[0].DST=(Uint32)&Dst[0];
        EDMA3Regs->PARAMSET[0].SRC_DST_BIDX=0x00000000;
        EDMA3Regs->PARAMSET[0].LINK_BCNTRLD=0x0000FFFF;
        EDMA3Regs->PARAMSET[0].SRC_DST_CIDX=0x00000000;
        EDMA3Regs->PARAMSET[0].CCNT=0x00000001;


        EDMA3Regs->ESRH=EDMA3Regs->ESRH|1; //Start EDMA copying

        TSK_sleep(100);
        printf("IPR:%X\n",EDMA3Regs->IPR);

    EDMA3 should copy data from Src to Dts. When I remove  bios.GBL.C64PLUSMAR224to255 = 0x0000ffff; from tcf file, EDMA3 copies data properly. Hovever, when  bios.GBL.C64PLUSMAR224to255 = 0x0000ffff; is present in tcf file, EDMA3 doesn't copy data but sets correspondent Transfer Complete bit in IPR register.

  • 0 in reply to Victor Ivanov
    Expert 1160 points

    The reason of my problem was absence of coherency between Cache and External memory. As TI explains me, when processor works with memory, cache controller is responsible for coherency between cache and external memory. But when EDMA works with external memory, a programmer has to stimulate cache controller to update cache. I added invalidation and write back commands to my code and it works fine now.