• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 99 subscribers
  • Views 359 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BT656 Display issue

Kaustubh Patankar
Prodigy 85 points
Hi All,
We are sending the digital YCC8 data through VENC module of DM365, data lines are getting interleaved. Display buffer is filled continuously with 576 lines.
 
Line 1 Top Filed
Line 3 Top Filed
Line 5 Top Filed
:
Line 1 Bottom Field
Line 3 Bottom Field
Line 5 Bottom Field
:
:
:
----> upto 288th line
Line 0 Top Field
Line 2 Top Field
Line 4 Top Filed
:
:
:
Line 0 Bottom Field
Line 2 Bottom Field
Line 4 Bottom Field
:
:
--->upto 576th line
 
Is it possible to capture continuously full top field (288 lines) then followed by bottom field (288 lines) at the receiving end?
 
Following are the configuration settings from application
1) Mode : PAL
2) Buffer type : V4L2_FIELD_INTERLACED
3) Width : 720
4) Height : 576
 
Additional register settings apart from the default kernel configurations are
1) YCCTL : 0x11 ---> to enable BT656 mode and CHM =1
2) SYNCCTL : 0x3
3) VMOD : 0x1043 -> to enable Ycc8
 
Note:- Default setting of TI for YCC16 is also sending the same data format
regard
Kaustubh
  • 0
    TI__Mastermind 43875 points

    Kaustubh,

    I am not quite sure what your question is? Can you clarify please?

    Your frame buffer should be continuous, just as if you were sending a progressive image to a display. The VENC will interlace the image as necessary.

    Is this your concern?

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 85 points

    Hi Steve,

    Yes you are correct. the interleaving is our concern. Is there any setting to avoid this and send the data as it is?

    regard

    Kaustubh

  • 0 in reply to Kaustubh Patankar
    TI__Mastermind 19985 points

    Kaustubh,

    BEcause you are using the PAL mode in VENC and taking the same timing on digital output, it is expected that you get field outputs instead of a full frame. But i dont understand why should this be a concern. As i understand, you have a FPGA to capture this digital output. Why don't you just capture the interleaved fields at the FPGA? or otherwise, you might want to change your digital out to remove PAL timing but configure your own timing to send out progressive data.

    Regards,

    Anshuman

    PS: Please mark this post as verified, if you think it has answered your question. Thanks.

  • 0 in reply to Kaustubh Patankar
    TI__Mastermind 43875 points

    Kaustubh,

    You can output frame buffer data in either interleaved or progressive format.

    I assume you simply want to get the progressive data from your frame buffer to your FPGA?

    If so, just use the 'normal' output format and not PAL.

    I am not sure on the SW configuration to achieve this, but it is straight forward.(I am a hardware guy, sorry)

    BR,

    Steve