This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3352: RXACTIVE default value

Part Number: AM3352


Hi,

What is the default value of Pad Control Register's "RXACTIVE" bit after reset?
As per the manual, it is written as "Set to 1 for input or output".
And the sample codes are also explicitly setting RXACTIVE bit to use it as an input function.

But, Low Power Design Guidelines(SPRAC74A)  below mentions that RXACTIVE is set by default after reset.

For the most part, unused interface pins can be left as no-connect.
However, since unused pins are often initialized at reset as inputs (RXACTIVE),
it is up to the software to mark the unused pins as RXACTIVE=0, which disables
the inputs and prevents unwanted input switching.

Please let me know if RXACTIVE = 1 by default?
and if it is required to set this bit through the software or else could be used without any settings
.
And with regards to Output, do we need to disable this bit if use a pin as output only?

Best Regards
Kummi

  • Hi,

    Kummi said:
    What is the default value of Pad Control Register's "RXACTIVE" bit after reset?

    See section 9.3.1.50 of the AM335x TRM Rev. P. You should note however, that pinmux will be modified by ROM code for pins thast are used in the SYSBOOT sequence.

    Kummi said:
    And with regards to Output, do we need to disable this bit if use a pin as output only?

    No, this is not necessary. In fact on serial interfaces like McSPI and I2C it's necessary to set RXACTIVE=1 on the clock pin, because this output signal is also used as a retiming input. The associated CONF_<module>_<pin>_RXACTIVE bit for the output clock must be set to 1 to enable the clock input back to the module.

  • Hi Biser,

    Thank you.

    One confirmation about the RXACTIVE requirement for RGMII's TX_CLK.

    As per the Schematics checklist and TRM,
    GPMC - GPMC_CLK/MMC - MMC_CLK/I2C - I2C_CLK/SPI - SPI_CLK/McASP peripherals
    required to have RXACTIVE bit set.
    processors.wiki.ti.com/.../AM335x_Schematic_Checklist

    Does it apply for RGMII peripheral also? Do we have to set RXACTIVE bit for TX_CLK?

    Best Regards.
  • I don't think it's necessary. This is purely an output path. There is a separate receive clock in RGMII.