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Interfacing NAND Flash with TMS320DM6467

tdipson
Prodigy 20 points

Other Parts Discussed in Thread: TMS320DM6467

First, let me start by saying that I am just a student working on senior design project with absolutely no experience with DSP hardware. So if I sound like a complete noobie please bear with me.

Our project is to design a circuit that is capable of real-time HD video (up to 1080p) compression using h.264 codec and stream it over 100 Mbps ethernet link. After crazy sleepless hours of reasearch, it appears TMS320DM6467 will be the processor of choice. Can somebody please comment on our choice of processor?

 Now to the more technicial question. We have started putting the circuit schematics together (oh boy!) and have decided to utilize 2 NAND flash chips; one for booting the DSP and the other for storage of codec algorithms.

From what we understand, we can use the same bus for the NAND I/Os, same line for the Ready/Busy (R/B#) signal, but different chip enable (CE) lines on the processor. The question now is do we have to use different pins on the processor for each NAND when connecting the CLE, ALE, WE#, and RE#  lines to the processor?  For example, can the CLE's or the ALE's of each NAND be tied together?

Also regarding, the R/B# signal, I read somewhere on another forum that it is better to use different GPIOs in order to be able to determine which NAND is busy. Any thoughts?

Thanks  

  • 0
    TI__Mastermind 41665 points

    tdipson said:
    Our project is to design a circuit that is capable of real-time HD video (up to 1080p) compression using h.264 codec and stream it over 100 Mbps ethernet link. After crazy sleepless hours of reasearch, it appears TMS320DM6467 will be the processor of choice. Can somebody please comment on our choice of processor?

    The DM6467 is the closest TI would have to this, however when you say 1080p you must be looking at 1080p30, as the 1080p60 display standard is not possible with the current DM6467 due to pixel clock and performance limitations.

    tdipson said:
    From what we understand, we can use the same bus for the NAND I/Os, same line for the Ready/Busy (R/B#) signal, but different chip enable (CE) lines on the processor. The question now is do we have to use different pins on the processor for each NAND when connecting the CLE, ALE, WE#, and RE#  lines to the processor?  For example, can the CLE's or the ALE's of each NAND be tied together?

    The chip enable line should seperate the two NAND devices, assuming they properly respect the chip enable signal, such that the other control lines can all be shared.

    tdipson said:
    Also regarding, the R/B# signal, I read somewhere on another forum that it is better to use different GPIOs in order to be able to determine which NAND is busy. Any thoughts?

    I am not sure what is being suggested here, though using a GPIO would give you more granularity as you suggest, so in theory it may be possible to alternate between reading from the NANDs as each is busy perhaps? This sounds like something that is not necessarily practical though, and I have certainly not seen it done before, most designs I have seen only use a single larger NAND as opposed to multiple smaller NANDs.

    In general during your schematic and layout design you may want to reference the DM6467 EVM collateral from Spectrum Digital, you may also want to obtain one of these boards for prototyping your system.