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Are you developing under CCS or Linux at the moment? If you are under CCS, we don't have existing examples at the moment.
I would suggest you to read the following to gain more understanding on the peripherals/devices you are using
http://www.ti.com/lit/gpn/ths8200
and
http://www.ti.com/litv/pdf/sprufg9c
HELLO ,I use th dvsdk 4.02 ,
my project is "dm365+th8200+ths7303" VGA output 1280x720p
I change the
davinci_platform.c ->davinci_enc_priv_setmode
and add the ths8200.c driver , i have already get 720p VGA video,
but i found the video clolor is wrong,my program is :
________________________________________________
dm365- >davinci_platform.c ->davinci_enc_priv_setmode
davinci_enc_set_720p(&mgr->current_mode);
davinci_enc_set_internal_hd(&mgr->current_mode);
ths8200_setval(THS8200_720P_60);
______________________________________________
davinci_platform.c ->davincidavinci_enc_set_720p
/* Reset video encoder module */
dispc_reg_out(VENC_VMOD, 0);
enableDigitalOutput(1);
dispc_reg_out(VENC_VDPRO, 0);
dispc_reg_out(VENC_VIDCTL, (VENC_VIDCTL_VCLKE | VENC_VIDCTL_VCLKP));
/* Setting DRGB Matrix registers back to default values */
dispc_reg_out(VENC_DRGBX0, 0x00000400);
dispc_reg_out(VENC_DRGBX1, 0x00000576);
dispc_reg_out(VENC_DRGBX2, 0x00000159);
dispc_reg_out(VENC_DRGBX3, 0x000002cb);
dispc_reg_out(VENC_DRGBX4, 0x000006ee);
/* Enable DCLOCK */
dispc_reg_out(VENC_DCLKCTL, VENC_DCLKCTL_DCKEC);
/* Set DCLOCK pattern */
dispc_reg_out(VENC_DCLKPTN0, 1);
dispc_reg_out(VENC_DCLKPTN1, 0);
dispc_reg_out(VENC_DCLKPTN2, 0);
dispc_reg_out(VENC_DCLKPTN3, 0);
dispc_reg_out(VENC_DCLKPTN0A, 2);
dispc_reg_out(VENC_DCLKPTN1A, 0);
dispc_reg_out(VENC_DCLKPTN2A, 0);
dispc_reg_out(VENC_DCLKPTN3A, 0);
dispc_reg_out(VENC_DCLKHS, 0);
dispc_reg_out(VENC_DCLKHSA, 1);
dispc_reg_out(VENC_DCLKHR, 0);
dispc_reg_out(VENC_DCLKVS, 0);
dispc_reg_out(VENC_DCLKVR, 0);
/* Set brightness start position and pulse width to zero */
dispc_reg_out(VENC_BRTS, 0);
dispc_reg_out(VENC_BRTW, 0);
/* Set LCD AC toggle interval and horizontal position to zero */
dispc_reg_out(VENC_ACCTL, 0);
/* Set PWM period and width to zero */
dispc_reg_out(VENC_PWMP, 0);
dispc_reg_out(VENC_PWMW, 0);
dispc_reg_out(VENC_CVBS, 0);
dispc_reg_out(VENC_CMPNT, 0);
/* turning on horizontal and vertical syncs */
dispc_reg_out(VENC_SYNCCTL, (VENC_SYNCCTL_SYEV | VENC_SYNCCTL_SYEH));
dispc_reg_out(VENC_OSDCLK0, 0);
dispc_reg_out(VENC_OSDCLK1, 1);
dispc_reg_out(VENC_OSDHADV, 0);
// __raw_writel(0xa, IO_ADDRESS(SYS_VPSS_CLKCTL));
if (cpu_is_davinci_dm355()) {
dispc_reg_out(VENC_CLKCTL, 0x11);
osd_write_left_margin(mode_info->left_margin);
osd_write_upper_margin(mode_info->upper_margin);
davinci_cfg_reg(DM355_VOUT_FIELD_G70);
davinci_cfg_reg(DM355_VOUT_COUTL_EN);
davinci_cfg_reg(DM355_VOUT_COUTH_EN);
}else if (cpu_is_davinci_dm365()) {
osd_write_left_margin(mode_info->left_margin);
osd_write_upper_margin(mode_info->upper_margin);
/* DM365 pinmux */
dispc_reg_out(VENC_CLKCTL, 0x10);
davinci_cfg_reg(DM365_VOUT_FIELD_G81);
davinci_cfg_reg(DM365_VOUT_COUTL_EN);
davinci_cfg_reg(DM365_VOUT_COUTH_EN);
/* Set VIDCTL to select VCLKE = 1,
VCLKZ =0, SYDIR = 0 (set o/p), DOMD = 0 */
dispc_reg_merge(VENC_VIDCTL, 1 << VENC_VIDCTL_VCLKE_SHIFT,
VENC_VIDCTL_VCLKE);
dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_VCLKZ_SHIFT,
VENC_VIDCTL_VCLKZ);
dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_SYDIR_SHIFT,
VENC_VIDCTL_SYDIR);
dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_YCDIR_SHIFT,
VENC_VIDCTL_YCDIR);
}else {
osd_write_left_margin(mode_info->left_margin);
osd_write_upper_margin(mode_info->upper_margin);
davinci_cfg_reg(DM644X_LOEEN);
davinci_cfg_reg(DM644X_GPIO3);
}
/* Set VENC for non-standard timing */
davinci_enc_set_display_timing(mode_info);
dispc_reg_out(VENC_HSDLY, 0);
dispc_reg_out(VENC_VSDLY, 0);
dispc_reg_out(VENC_YCCCTL, 0X0);
dispc_reg_out(VENC_VSTARTA, 0);
/* Enable all VENC, non-standard timing mode, master timing, HD,
progressive
*/
if (cpu_is_davinci_dm355()) {
dispc_reg_out(VENC_VMOD, (VENC_VMOD_VENC | VENC_VMOD_VMD));
} else {
dispc_reg_out(VENC_VMOD,
(VENC_VMOD_VENC | VENC_VMOD_VMD));
}
dispc_reg_out(VENC_LCDOUT, 0);
________________________________________-
th8200.c
int ths8200_setval(enum ths8200_modes mode)
{
int err = 0, disable = 0;
if (ths8200_client == NULL)
return 0;
switch (mode) {
case THS8200_720P_60:
printk("ths8200 set THS8200_720P_60\n ");
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CHIP_CTL, 0x01);//WR_REG,THS8200,0x01,0x03,0x01 // chip_ctl frequency range=high
//YCbR to RGB
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_R11, 0x81);//WR_REG,THS8200,0x01,0x04,0x81 // csc_ric1
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_R12, 0xD5);//WR_REG,THS8200,0x01,0x05,0xD5 // csc_rfc1
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_R21, 0x00);//WR_REG,THS8200,0x01,0x06,0x00 // csc_ric2
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_R22, 0x00);//WR_REG,THS8200,0x01,0x07,0x00 // csc_rfc2
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_R31, 0x06);//WR_REG,THS8200,0x01,0x08,0x06 // csc_ric3
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_R32, 0x29);//WR_REG,THS8200,0x01,0x09,0x29 // csc_rfc3
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_G11, 0x04);//WR_REG,THS8200,0x01,0x0A,0x04 // csc_gic1
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_G12, 0x00);//WR_REG,THS8200,0x01,0x0B,0x00 // csc_gfc1
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_G21, 0x04);//WR_REG,THS8200,0x01,0x0C,0x04 // csc_gic2
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_G22, 0x00);//WR_REG,THS8200,0x01,0x0D,0x00 // csc_gfc2
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_G31, 0x04);//WR_REG,THS8200,0x01,0x0E,0x04 // csc_gic3
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_G32, 0x00);//WR_REG,THS8200,0x01,0x0F,0x00 // csc_gfc3
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_B11, 0x80);//WR_REG,THS8200,0x01,0x10,0x80 // csc_bic1
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_B12, 0xBB);//WR_REG,THS8200,0x01,0x11,0xBB // csc_bfc1
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_B21, 0x07);//WR_REG,THS8200,0x01,0x12,0x07 // csc_bic2
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_B22, 0x42);//WR_REG,THS8200,0x01,0x13,0x42 // csc_bfc2
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_B31, 0x00);//WR_REG,THS8200,0x01,0x14,0x00 // csc_bic3
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_B32, 0x00);//WR_REG,THS8200,0x01,0x15,0x00 // csc_bfc3
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_OFFS1, 0x14);//WR_REG,THS8200,0x01,0x16,0x14 // csc_offset1
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_OFFS12, 0xAE);//WR_REG,THS8200,0x01,0x17,0xAE // csc_offset12
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_OFFS23, 0x8B);//WR_REG,THS8200,0x01,0x18,0x8B // csc_offset23
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSC_OFFS3, 0x15);//WR_REG,THS8200,0x01,0x19,0x15 // csc_offset3
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DATA_CNTL, 0x13);//WR_REG,THS8200,0x01,0x1C,0x53 // dman_cntl 20bit 422
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_Y_SYNC1_LSB, 0x00);//WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_Y_SYNC2_LSB, 0x00);//WR_REG,THS8200,0x01,0x1E,0x00 // dtg_y_sync2
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_Y_SYNC3_LSB, 0x00);//WR_REG,THS8200,0x01,0x1F,0x00 // dtg_y_sync3
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_CBCR_SYNC1_LSB, 0x00);//WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_CBCR_SYNC2_LSB, 0x00);//WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_CBCR_SYNC3_LSB, 0x00);//WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_Y_SYNC_MSB, 0x2A);//WR_REG,THS8200,0x01,0x23,0x2A // dtg_y_sync_upper
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_CBCR_SYNC_MSB, 0x2A);//WR_REG,THS8200,0x01,0x24,0x2A // dtg_cbcr_sync_upper
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_A, 0x28);//WR_REG,THS8200,0x01,0x25,0x28 // dtg_spec_a
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_B, 0x6E);//WR_REG,THS8200,0x01,0x26,0x6E // dtg_spec_b
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_C, 0x28);//WR_REG,THS8200,0x01,0x27,0x28 // dtg_spec_c
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_D_LSB, 0x04);//WR_REG,THS8200,0x01,0x28,0x04 // dtg_spec_d
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_D1, 0x00);//WR_REG,THS8200,0x01,0x29,0x00 // dtg_spec_d1
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_E_LSB, 0x04);//WR_REG,THS8200,0x01,0x2A,0x04 // dtg_spec_e
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_DEH_MSB, 0xC0);//WR_REG,THS8200,0x01,0x2B,0xC0 // dtg_spec_h_msb
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_H_LSB, 0x00);//WR_REG,THS8200,0x01,0x2C,0x00 // dtg_spec_h_lsb
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_I_MSB, 0x00);//WR_REG,THS8200,0x01,0x2D,0x00 // dtg_spec_i_msb
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_I_LSB, 0x00);//WR_REG,THS8200,0x01,0x2E,0x00 // dtg_spec_i_lsb
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_K_LSB, 0x6E);//WR_REG,THS8200,0x01,0x2F,0x6E // dtg_spec_k_lsb
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_K_MSB, 0x00);//WR_REG,THS8200,0x01,0x30,0x00 // dtg_spec_k_msb
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_K1, 0x00);// WR_REG,THS8200,0x01,0x31,0x00 // dtg_spec_k1
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_G_LSB, 0x00);// WR_REG,THS8200,0x01,0x32,0x00 // dtg_speg_g_lsb
i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_G_MSB, 0x00);// WR_REG,THS8200,0x01,0x33,0x00 // dtg_speg_g_msb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_TOT_PIXELS_MSB, 0x06);//WR_REG,THS8200,0x01,0x34,0x03 // dtg_total_pixel_msb adjust for various graphics formats
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_TOT_PIXELS_LSB, 0x72);//WR_REG,THS8200,0x01,0x35,0x5A // dtg_total_pixel_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_FLD_FLIP_LINECNT_MSB, 0x080);//WR_REG,THS8200,0x01,0x36,0x80 // dtg_linecnt_msb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_LINECNT_LSB, 0x01);//WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_MODE, 0x87);//WR_REG,THS8200,0x01,0x38,0x87 // dtg_mode VESA Slave
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_FRAME_FIELD_SZ_MSB, 0x27);//WR_REG,THS8200,0x01,0x39,0x27 // dtg_frame_field_msb adjust for various graphics formats
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_FRAME_SZ_LSB, 0xEE);//WR_REG,THS8200,0x01,0x3A,0x0D // dtg_frame_size_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_FIELD_SZ_LSB, 0xFF);//WR_REG,THS8200,0x01,0x3B,0xFF // dtg_field_size_lsb
//CSM setup to map YCbCr to FS RGB
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_CLIP_GY_LOW, 0x40);//WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_CLIP_BCB_LOW, 0x40);//WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_CLIP_RCR_LOW, 0x40);//WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_CLIP_GY_HIGH, 0x53);//WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_CLIP_BCB_HIGH, 0x3F);//WR_REG,THS8200,0x01,0x45,0x3F // csm_clip_bcb_high
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_CLIP_RCR_HIGH, 0x3F);//WR_REG,THS8200,0x01,0x46,0x3F // csm_clip_rcr_high
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_SHIFT_GY, 0x40);//WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_SHIFT_BCB, 0x40);//WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_SHIFT_RCR, 0x40);//WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_GY_CNTL_MULT_MSB, 0xFC);//WR_REG,THS8200,0x01,0x4A,0xFC // csm_mult_gy_msb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_MULT_BCB_RCR_MSB, 0x44);//WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_MULT_GY_LSB, 0xAC);//WR_REG,THS8200,0x01,0x4C,0xAC // csm_mult_gy_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_MULT_BCB_LSB, 0xAC);//WR_REG,THS8200,0x01,0x4D,0xAC // csm_mult_bcb_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_MULT_RCR_LSB, 0xAC);//WR_REG,THS8200,0x01,0x4E,0xAC // csm_mult_rcr_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CSM_MULT_RCR_BCB_CNTL, 0xFF);//WR_REG,THS8200,0x01,0x4F,0xFF // csm_mode
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_HLENGTH_LSB, 0x28);//WR_REG,THS8200,0x01,0x70,0x40 // dtg_hlength_lsb adjust HSOUT width for various formats
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x01);//WR_REG,THS8200,0x01,0x71,0x03 // dtg_hdly_msb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_HLENGTH_HDLY_LSB, 0x04);//WR_REG,THS8200,0x01,0x72,0x31 // dtg_hdly_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_VLENGTH1_LSB, 0x05);//WR_REG,THS8200,0x01,0x73,0x07 // dtg_vlength_lsb adjust VSOUT width for various formats
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x02);//WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_VDLY1_LSB, 0xED);//WR_REG,THS8200,0x01,0x75,0x07 // dtg_vdly_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_VLENGTH2_LSB, 0x00);//WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07);//WR_REG,THS8200,0x01,0x77,0xC7 // dtg_vdly2_msb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_VDLY2_LSB, 0xFF);//WR_REG,THS8200,0x01,0x78,0xFF // dtg_vdly2_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_HS_IN_DLY_MSB, 0x00);//WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb adjust for horizontal alignment
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_HS_IN_DLY_LSB, 0x0A);//WR_REG,THS8200,0x01,0x7A,0x0F // dtg_hs_in_dly_lsb
// err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_HS_IN_DLY_MSB, 0x00);//WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb adjust for horizontal alignment
// err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_HS_IN_DLY_LSB, 0x32);//WR_REG,THS8200,0x01,0x7A,0x0F // dtg_hs_in_dly_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_VS_IN_DLY_MSB, 0x00);//WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb adjust for vertical alignment
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_VS_IN_DLY_LSB, 0x00);//WR_REG,THS8200,0x01,0x7C,0x00 // dtg_vs_in_dly_lsb
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_CNTL, 0x5B);//WR_REG,THS8200,0x01,0x82,0x5B // pol_cntl HS/VSin ++, HS/VSout++, FID -
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CGMS_CNTL_HEADER, 0x00);//WR_REG,THS8200,0x01,0x83,0x00
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CGMS_PAYLOAD_MSB, 0x00);//WR_REG,THS8200,0x01,0x84,0x00
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CGMS_PAYLOAD_LSB, 0x00);//WR_REG,THS8200,0x01,0x85,0x00
err = i2c_smbus_write_byte_data(ths8200_client, THS8200_CHIP_CTL, 0x00);
mdelay(50);
err = i2c_smbus_write_byte_data(ths8200_client, THS8200_CHIP_CTL, 0x01);
break;
default:
/* disable all channels */
printk("ths8200_colorbar \n");
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CHIP_CTL, 0x23);
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_MODE, 0x87);//WR_REG,THS8200,0x01,0x38,0x86 // dtg_mode VESA master
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG2_CNTL, 0x5B);//WR_REG,THS8200,0x01,0x82,0x5B // pol_cntl HS/VSin ++, HS/VSout++, FID -
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_VESA_CBAR_SIZE, 0x80);
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_DEH_MSB, 0x00);
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_DTG1_SPEC_E_LSB, 0xC0);
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CHIP_CTL, 0x22);
mdelay(50);
err |=i2c_smbus_write_byte_data(ths8200_client, THS8200_CHIP_CTL, 0x23);
disable = 1;
break;
}
if (err)
{
printk("reset th8200 error!\n");
return err;
}
return err;
}
i don't know why the color is wrong? please help me .
