Tool/software: TI-RTOS
Hi,
My question might be awkward.
Still I would like to understand the difference in phase here for the SPI Clock:
The generic nomenclature that I have seen for the SPI phase is either the data latching on the rising/falling edge of the SPI clock.
In the TI AM437x, from the TRM, when I see the configuration register, I see the below terminology:
SPICLK phase
0h (R/W) = Data are latched on odd numbered edges of SPICLK.
1h (R/W) = Data are latched on even numbered edges of SPICLK.
My gut feeling is- odd edges are falling edges while the even edges are raising edges.
I would like to understand this and get a confirmation on this from the experts.
Thanks in advance.
