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66AK2H14: HyperLink bootmode Ref Clk Setting

Jack Carter
Prodigy 190 points
Part Number: 66AK2H14
Other Parts Discussed in Thread: CDCM6208

Table 10-14. HyperLink Boot Device Configuration Field Descriptions, page 195 of the 66AK2H14 Product Manual, indicates that bits 15-14 represent the "HyperLink reference clock configuration". The only valid entries are shown as follows:

0 = 125 MHz

1 = 156.25 MHz

2-3 = Reserved

On the EVMK2H14 Development Board the HyperLink interface is driven by a 312.5 MHz clock. What is the correct setting for the above register bits to support HyperLink bootmode for this EVM?

  • 0
    TI__Guru**** 161600 points
    Hi,

    I am looking into this. I will post my findings here.

    Best Regards,
    Yordan
  • 0
    TI__Mastermind 42545 points
    Hi Jack,
    The EVM does not support Hyperlink boot as delivered. Hyperlink boot could be supported as a secondary boot device allowing the clock to be configured correctly using the available reference clock.
    Regards,
    Bill
  • 0 in reply to Bill Taboada
    Prodigy 190 points

    Thanks for the update. That makes a lot of sense now. If I were going to build a board with the same KeyStone II device would the HyperLink bootmode be viable if the Reference Clock were 156.25MHz?

  • 0 in reply to Jack Carter
    TI__Mastermind 42545 points
    Hi Jack,
    Hyperlink boot is limited due to the smaller number of components that support Hyperlink. I know that some customers are using Hyperlink as a communications channel between components but few are using it as a boot interface. I can be a difficult interface to get working correctly. PCIE is much more common.
    You may want to consider the two stage boot concept. An inexpensive I2C or SPI memory could be used as your primary boot device. That boot code could be used to configure and start your serdes interface and then to initiate the boot. This is a common approach used by customers to ensure that the device will partially boot even if the serdes boot interface isn't available.
    In addition you could modify your EVM. The 312.5MHz reference clock is generated by the CDCM6208 which can be easily reprogrammed to generate 156.25MHz. You would have to modify the BMC code to include the HyperLink boot modes settings that you want as one of the eight user programmable boot modes as well. Both those changes are possible although I don't know that they have every been tested on the EVM.
    Regards,
    Bill
  • 0 in reply to Bill Taboada
    Prodigy 190 points
    Thanks Bill,
    I have already modified the BMC to include a DSP Bootmode which spawned this set of questions initially. I have also been looking at the BMC source and determined that I can unlock the "clkreg" command. I believe I should be able to configure CLK3 output U0 to generate a 156.25MHz clock instead of the default 312.5MHz. If this all pans out then I will rebuild the BMC image and reflash with the correct settings. In addition, I have already experimented with multi-stage SPI boot and EMIF NAND boot so there are certainly other options available.

    Thanks for your support.

    Jack
  • 0 in reply to Jack Carter
    Prodigy 190 points
    Hi Bill,

    I was able to successfully modify the reference clock configuration through the BMC. Just for the record here are the settings that I made to change the reference clock from 312.5Mhz to 156.25MHz.

    (1) Launch a terminal emulator and connect to micro-controller serial port on the EVM. When properly connected the EVM boot messages will scroll upon power-up and a prompt will be displayed.
    (2) Enter the following to enable the 'clkreg' command.
    BMC> hwdbg cmd clkreg
    (3) Disable the clock output for HyperLink 0 & 1.
    BMC>clkreg 3.5 0x0001
    (4) Change the clock divisor for the HyperLink reference clock. Doubling the divisor will cut the clock rate in half. Note, that the actual divisor is one greater than the register setting. Hence, a register value of 1 results in a divisor of 2. A register value of 3 will provide the needed divide by 4 value.
    BMC>clkreg 3.6 0x0003
    (5) Enable the clock ouput.
    BMC>clkreg 3.5 0x0023

    Obviously lots of details missing from the above sequence but this did correct the problem. I was able to probe the output of U19, the CDCM6208 part responsible for the HyperLink reference clocks, and observe that the output was in fact changed from 312.5MHz to 156.25MHz. Once this change was made I could successfully establish a HyperLink connection between the two EVMs and copy data from the "master" device to several different regions of the "slave" device configured in HyperLink bootmode. I'm currently attempting to rebuild the BMC image that is flashed on the EVM so that the default configuration for the HyperLink reference clocks will be 156.25MHz.

    Thanks again for your support.

    Regards,

    jack
  • 0 in reply to Jack Carter
    TI__Mastermind 42545 points

    Hi Jack,

    That's great to hear and I appreciate you sharing your process with the forum. We attempted to build some flexibility into the EVM but I think you're the first person to try this. Let me know if I can help further. 

    Regards,

    Bill