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Linux/AM3354: Ethernet connection in u-boot

Alfonso Kame
Prodigy 30 points
Part Number: AM3354


Tool/software: Linux

Hi,
Refering the thread e2e.ti.com/.../181692 , we are facing a similar issue for weeks here.
The RGMII2 pins have been configured for ethernet.


I just can't ping the host from uboot. The custom device indicate that the link is up.
After configuring the 100M connection, I measured the RGMII2_TCLK frequency. I got roughly 12,5 MHZ.

1. Which dpll structure or variable/divider should I adapt to get 25 MHZ? I assumed this is the frequency to reach.
2. How can I measure the CORE_CLOCKOUTM5 frequency? by only reading a specific register?

Thank you very much

Kind regards


  • 0
    TI__Guru**** 170625 points

    Hi Alfonso,

    Do you use custom board? Do you use TI SDK? If yes, which version? Can you provide full console log output?

    Alfonso Kame said:
    1. Which dpll structure or variable/divider should I adapt to get 25 MHZ? I assumed this is the frequency to reach.
    2. How can I measure the CORE_CLOCKOUTM5 frequency? by only reading a specific register?

    I think setting CORE_CLKOUTM5 to 250MHz should be enough for getting 25MHz clock on the RGMII_TCLK pin output. CORE_CLKOUTM5 goes through fixed dividers of / 5 and /2 to produce 25MHz clock for MHZ_50_CLK signal that is used for RGMII 100 Mbps. See AM335x TRM, Figure 8-10. Core PLL

    For getting CORE_CLKOUTM5 frequency, you should dump Core PLL registers values.

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 30 points

    Hi Pavel,

    thanks very much for the reply.

    Actually I'm porting the bootloader to a custom board deriving from the am335x-evm starter kit.

    The Uboot version is: U-Boot 2016.05-00330-ga3d7672-dirty

    Here is the console output:

    U-Boot 2016.05-00330-ga3d7672-dirty (Jul 27 2017 - 11:57:06 +0200)                                                                    
                                                                                                                                          
    CPU  : AM335X-GP rev 2.1                                                                                                              
    Model: CUSTOM V1.0                                                                                                               
           Watchdog enabled                                                                                                               
    DRAM:  1 GiB                                                                                                                          
    mpu max Freq: 550 - core max Freq: 1000                                                                                               
    NAND:  1024 MiB                                                                                                                       
    MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1                                                                                                 
    SF: Detected MX25L12805 with page size 256 Bytes, erase size 64 KiB, total 16 MiB                                                     
    Net:   cpsw                                                                                                                      
                                                                           
    Press SPACE to abort autoboot in 4 seconds                                                                                            
    SP_U_BOOT # ping 192.168.2.13                                                                                                        
    link up on port 0, speed 100, full duplex                                                                                             
    Using cpsw device                                                                                                                     
                                                                                                                                          
    ARP Retry count exceeded; starting again                                                                                              
    ping failed; host 192.168.2.13 is not alive                                                                                           
    SP_U_BOOT # ping 192.168.2.13                                                                                                        
    link up on port 0, speed 100, full duplex                                                                                             
    Using cpsw device                                                                                                                     
                                                                                                                                          
    ARP Retry count exceeded; starting again                                                                                              
    ping failed; host 192.168.2.13 is not alive                                                                                           
    SP_U_BOOT #                               

    Here is the dump of the core pll register:

    md.w 0x44E00490 1 --> clkmode_dpll
    44e00490: 0007                                       ..

    md.w 0x44E0045C 1  --> idlest_dpll
    44e0045c: 0001                                       ..

     md.w 0x44E00468 1  --> clksel_dpll
    44e00468: e817                                       ..

    md.w 0x44E00480 1  --> div_m4_dpll
    44e00480: 022a                                       *.


    md.w 0x44E00484 1  --> div_m5_dpll
    44e00484: 0228                                       (.

    md.w 0x44E004D8 1  --> div_m6_dpll
    44e004d8: 0004                                       ..

    From this output, I would say the register look OK. I'am wondering why I can't get the 25MHZ from the TXCLK (RGMII2_TCLK)

    Thank you very much Pavel

    King Regards

  • 0 in reply to Alfonso Kame
    TI__Guru**** 170625 points

    Can you also measure the clock frequency you have on pin rgmii1_tclk?  In u-boot RGMII1 is enabled by default, so you see port 0 in the log.


    What main oscillator you have on your custom board? In AM335x StarterKit we have 24MHz OSC0 (main oscillator) so input clock frequency of CorePLL (CLKINP) is 24MHz. Check also you have correct SYSBOOT[15:14] configuration.

    The formula for CorePLL CLKDCOLDO output clock is:

    CLKDCOLDO = 2 * M/(N+1) * CLKINP = 2 * 232/(23+1) * 24 = 464MHz. Then it goes through div of 8, thus produce 58MHz (not 250MHz as we expect).

    CM_CLKSEL_DPLL_CORE[6:0] DPLL_DIV = 0x17 (N = 23)

    CM_CLKSEL_DPLL_CORE[18:8] DPLL_MULT = 0xE8 (M = 232)

    CM_DIV_M5_DPLL_CORE[4:0] HSDIVIDER_CLKOUT2_DIV = 0x8 (div 8)


    Please play with your HSDIVIDER_CLKOUT2_DIV value and see how the frequency on RGMII2_TCLK pin will change.

    See also below e2e thread:

    Regards,
    Pavel