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RTOS/AM5728: PCIe evaluation issue

Ernest Cho
Expert 3191 points
Part Number: AM5728


Tool/software: TI-RTOS

Hello Champs,

One of my customer made their 1st AM5728 target board.
They would like to communicate their target board and WIN7 PC via PCIe.
But now they get in trouble with setting the PCIe.

Their test environments are as below.

Environments

HW referred AM5728 IDK
PCIe x1 Lane, Gen2
CCS : 6.1.2
PDK ver : pdk_am57xx_1_0_3

CCS project

- CCS project based on,
PCIE_idkAM572x_wSoCFile_armExampleProject

Symptom

After ‘enable link training’ PCIe register is reset.
LTSSM_EN bit force set to 1 but cleared to 0.
PCIe Tx signal is not output continuously.

In short, they found this bit is cleared even they set the bit : PCIECTRL_TI_CONF_DEVICE_CMD.LTSSM_EN

And the PCIe Tx is out shortly at the initial operation and do not signal out continuously.
And when they turn on the LTSSM_EN bit, then Tx signal out continuously.

Q1 : Why LTSSM_EN bit is cleared? Customer is evaluated v1.0.7 too but symptom is same.

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points
    Hi,

    I thought we discussed this in the past:

    TI IDK EVM is primarily wired as PCIE RC. You have to use your own designed board for testing with Windows PC as PCIE RC.

    -For HW, the board needs to be designed to use the PCIe reference clock from host PC.

    - For the SW, it needs to change it to accept clock from outside:


    In C:\ti\pdk_am57xx_1_0_x\packages\ti\drv\pcie\example\sample\am57x\src\pcie_sample_board.c. Function PlatformPCIESS1PllConfig(), one needs to change the PCIE clock to receive from ACS.

    /*PCIe Tx and Rx Control of ACSPCIe 0x4A003C14, bit17:16 0x0: power down, 0x1: Tx, 0x2: Rx*/
    HW_WR_FIELD32(SOC_SEC_EFUSE_REGISTERS_BASE + CSL_CONTROL_CORE_SEC_SMA_SW_6,
    CSL_CONTROL_CORE_SEC_SMA_SW_6_PCIE_TX_RX_CONTROL, 0x02U);

    /*Locking APLL to 2.5GHz with 100MHz input*/
    regVal = HW_RD_REG32(SOC_CKGEN_CM_CORE_BASE + CM_CLKMODE_APLL_PCIE);

    HW_SET_FIELD(regVal, CM_CLKMODE_APLL_PCIE_CLKDIV_BYPASS,
    CM_CLKMODE_APLL_PCIE_CLKDIV_BYPASS_PCIEDIVBY2_BYPASS_1);

    HW_SET_FIELD(regVal, CM_CLKMODE_APLL_PCIE_REFSEL,
    CM_CLKMODE_APLL_PCIE_REFSEL_CLKREF_ACSPCIE);

    Regards, Eric
  • 0 in reply to lding
    TI__Expert 3191 points
    Hi Eric,
    That's correct, it has been talked via email.
    Thank you.
    Ernest.