Hi,
Is there setting to reduce jitter of tDH, tDS of DDQ DQS?
When REFCLK is 20 MHz, the setting value of default DDR PLL on u-boot is as follows.
M = 266
N = 4
M2 = 2
DDR clock = 20 × M × 1 / (N + 1) × 1 / M 2= 532 MHz
In addition to changing the DDR PLL setting value, please let me know if there is a way to reduce that jitter.
Best Regards,
Shigehiro Tsuda
