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RTOS: AM57X interface questions

Matthias Paul
Prodigy 20 points

Tool/software: TI-RTOS

Dear community,

I'm new to TI Sitara, looking for a AM57x integration. Here are some basic questions about peripherals / interfaces:

  1. I'd like to incorporate EtherCat slave. As far as I understood, the real-time capabilities of a PRU-ICSS chip are used. How many instances of the PRUs are required?
  2. On top of that, an additional Ethernet connection should be applied. Which part of the system is handling the data RX/TX?
  3. I'd like to interface a FPGA, but I'm limited to a high-speed serial protocol like SPI. My goal is to transfer 64 bits of data (generated by DSPs) every 1 µs. In the documentation it is said that QSPI is only used to read data from SD/MMC. I need the other way around, only sending data out. Is there some way to achieve this, probably by using the 2nd PRU-ICSS bit-banging a I/O port? If so, is it possible to estimate the max. baud rate?
  4. Is the system's IPC capable of doing 1 MHz send/receive intervals (e.g. by interrupt) between DSP and PRU-ICSS or Cortex-M4? I doubt the RTOS IPC can handle this speed, am I wrong?
  5. Is it possible to have a M4 directly access the CANbus peripherals?

Thank you for reading,
Paul

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Expert 7570 points
    Hi Matthias

    In general we recommend submitting separate posts on different topics to ensure we get the correct people to support your questions.
    I can answer your EtherCAT questions.

    1.I'd like to incorporate EtherCat slave. As far as I understood, the real-time capabilities of a PRU-ICSS chip are used. How many instances of the PRUs are required?

    The EtherCAT slave requires the use of 2 PRUs of 1 ICSS.

    2.On top of that, an additional Ethernet connection should be applied. Which part of the system is handling the data RX/TX?

    Let me help out one of my associates.
    The AM572x IDK can support an additional Ethernet on the CPSW interface. This interface is described in the IDKEVM User Guide, AM572 TRM and data sheet.
    www.ti.com/.../sprui64
    www.ti.com/.../spruhz6
    www.ti.com/.../am5728

    The AM571x IDK can support an additional Ethernet on the CPSW interface or on the other ICSS. These interfaces are described in the IDKEVM User Guide, AM572 TRM and data sheet.
    www.ti.com/.../sprui97
    www.ti.com/.../spruhz7
    www.ti.com/.../am5718

    David
  • 0 in reply to David Zaucha
    Prodigy 20 points
    After going through some of the documentation, I understood better how the chip works. Thank you for the links, David.

    Question 3 has somewhat changed as I'm not looking for a hardware-implemented QuadSPI anymore. I'd rather use same very basic parallel protocol (means: 8 TX lines, no RX line, a clock line, and a chip select line). This makes it much easier to put a full byte on 8 neighbouring I/O lines. Still the question is, how fast can different processors signal each other. Or is it probably much easier to send data which has been calculated by a DSP directly by the DSP to the parallel I/O?