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AM3358: McSPI chip-select control

Sung-IL
Mastermind 31540 points

Part Number: AM3358

Dear Champs,

As my customer found the delay between CS and SPI clock were too long and out of spec, they have worked to reduce this delay and reduced it thanks to below e2e.

To reduce this delay time, they set the 'INITDLY' values to '0' as above e2e mentioned in below.

But, they found CS signal was swing(Low/High) along with each words as below. Is it possible to stop this swing in CS signal and stay it to low during SPI communication?

e.g. they want to make below by reducing latency.

Thanks and Best Regards,

SI.

  • 0
    TI__Guru**** 393215 points
    Hi,

    See section 24.3.2.6.2 of the AM335x TRM Rev. P.
  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 31540 points
    Hi Biser,

    I found there was one more thing they have done and it was 'SINGLE' mode bit to '0' - e.g. Multi Channel Master mode.
    Their target latency was under 50ns.
    They can achieve only 10us delay time with SINGLE channel master mode(SINGLE = 1) even when they set INITDLY = 0, but they can achieve under 50ns delay with multi channel master mode by SINGLE = 0.

    It seemed similar result was observed in below e2e, and last reply was

    "the delay-change did not take effect unless we also cleared the OMAP2_MCSPI_MODULCTRL_SINGLE field."

    e2e.ti.com/.../550738


    Is there anything else to make SINGLE channel mode except setting 'SINGLE' field to '1'?
    or is it natural the latency was bigger in SINGLE channel master mode than MULTI channel master mode?

    Thanks and Best Regards,
    SI.
  • 0 in reply to Sung-IL
    TI__Mastermind 31540 points

    Hi,

    When I checked 24.3.2.6.2 of TRM(ver.p), I found below and am trying to reduce the time between SPIEN signal activated and the start of transfer. But I could not find what is the 'transmitter register' and 'receive register'. is it 'FIFO transmit buffer register' and 'FIFO receive buffer register'?

    Could you please provide guide how we can start transfer immediately to reduce time gap with SPIEN signal?

    With this, do you think we can reduce the time gap between SPIEN signal activated and start of transfer as low as multi-channel master mode?

    Thanks and Best Regards,

    SI.

  • 0 in reply to Sung-IL
    TI__Mastermind 31540 points
    Hi,

    Is there any update on this?
    I could not find any reason why the delay time of single channel master was different with multi-channel master mode case. Am I right?

    Thanks and Best Regards,
    SI.
  • 0 in reply to Sung-IL
    TI__Genius 16030 points

    Hi SI,

    Sorry for the delay.  I am looking into this issue.  However, it may be a few days before I have an answer. 

    To clarify your question about the ‘transmitter register’ and ‘receive register’ in section 24.3.2.6, these refer to “… the status of the MCSPI_TXx register (the SPIm.MCSPI_CHxSTAT[1] TXS bit), the status of the MCSPI_RXx register (the SPIm.MCSPI_CHxSTAT[0] RXS bit), and the defined mode (the SPIm.MCSPI_CHxCONF[13:12] TRM bit field) of the channel enabled.”

    Regards,

    Melissa