AM4376: LPDDR2 layout rules

shigehiro tsuda

Mastermind 9490 points

Part Number: AM4376

Hi,

Is it necessary to have equal length wiring between the DQS [x] group and the CK-ADDR_CTRL group?

Best Regards,
Shigehiro Tsuda

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Hi,

Each DQS clock net class is length matched to its associated DQ signal net class. Length matching is only done within a byte. Length matching across bytes is not required. Length matching across DQ and ADDR_CTRL net classes is also not required.

0 Biser Gatchev-XID over 8 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

My initial response is inaccurate: For LPDDR2 it is required to have length matching between the DQS net class and the DDR CLK to meet tDQSS.

0 shigehiro tsuda over 8 years ago in reply to Biser Gatchev-XID

Mastermind 9490 points

Hi Biser,

Thank you for quick reply.
I understood that it is required to have length matching between the DQS net class and the DDR CLK .

Best Regards,
Shigehiro Tsuda

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AM4376: LPDDR2 layout rules