TMS320C6678: Binary deployment at runtime

Giovambattista Astorino

Intellectual 290 points

Part Number: TMS320C6678

Hi all,

I'm trying to create a simple project in which core0 loads a program

into the other cores. The program loaded is the same executed by

Core0 (_c_int00). I found several example on the forum which was

almost the same so i wrote my code:

Core0:

1. Writing of _c_int00 on every core magic address

2. KICK0 and KICK1 unlock

3. Writing of IPCGR register on every core

The program, once loaded on slave core 3 should blink a led on

GPIO 10.

It seems that the IPC interrupt is not triggered. I attach my code to the topic.

Fullscreen 5504.main.c Download

//#include <boot_bench.h>

#include "ti/csl/csl_gpioAux.h"
#include <ti/platform/evmc6678l/platform_lib/include/evmc66x_gpio.h>



//KICK registers
#define KICK0             		(0x2620038)
#define KICK1              		(0x262003C)

//Magic address of each core
#define MAGIC_ADDR          	0x0087FFFC
#define BOOT_MAGIC_ADDR(x)		(MAGIC_ADDR+(1<<28)+(x<<24))

//Write to address function
#define DEVICE_REG32_W(x,y)   	*(volatile uint32_t *)(x)=(y)
//Read from address function
#define DEVICE_REG32_R(x)    	(*(volatile uint32_t *)(x))

//Trigger IPC interrupt
#define IPCGR(x)            	(0x02620240 + x*4)

#define NUM_OF_CORES			(8)


//Core number
extern cregister volatile unsigned int DNUM;

extern far uint32_t _c_int00;

CSL_GpioHandle GPIO_handle = NULL;

/******************************************************************************
 * Function:    main
 ******************************************************************************/
void main ()
{

	GPIO_handle = CSL_GPIO_open(0);

	CSL_GPIO_setPinDirOutput(GPIO_handle, 10);



	//Executed only by master core
	if (DNUM==0)

	{

		uint32_t loop;
		uint32_t core;

		for (core = 1; core < 8; core++)
		 {

			DEVICE_REG32_W(BOOT_MAGIC_ADDR(core), (uint32_t)&_c_int00);


			for (loop = 0; loop < 1000; ++loop) {}//delay

		 }


		DEVICE_REG32_W(KICK0, 0x83e70b13);
		DEVICE_REG32_W(KICK1, 0x95a4f1e0  );

		for (core = 1; core < 8; core++)
		 {

			DEVICE_REG32_W(IPCGR(core), 1);

			for (loop = 0; loop < 1000; ++loop) {}//delay

		 }

	}


	int i;
	while(1)
	{
		if (DNUM==3)	//Core 3 toggles a led every 0.5 sec @ 1 GHz

		{

	    CSL_GPIO_setOutputData(GPIO_handle, 10);


	    for (i=0; i<10000000; i++)
	    {

	    }
	    CSL_GPIO_clearOutputData(GPIO_handle, 10);

	    for (i=0; i<10000000; i++)
	    {

	    }

		}

	}


}

Can someone please help me?

Thanks

over 8 years ago

0 Yordan Kovachev over 8 years ago

TI__Guru**** 161600 points

Hi,

I've notified the sw team. Feedback will be posted here.

Best Regards,
Yordan

0 Alberto Chessa over 8 years ago

Mastermind 6670 points

Hi,

Where you place the executable code and data? L2RAM, MCSM?

0 Giovambattista Astorino over 8 years ago in reply to Alberto Chessa

Intellectual 290 points

There is no external executable (such as .h file with bootable code). The program executed by Core0, and then loaded to slave Cores, is stored in L2RAM. I hope I answered your question

0 Alberto Chessa over 8 years ago in reply to Giovambattista Astorino

Mastermind 6670 points

Hi,

The L2RAM is per-core private (same logical addresses but different physical memory). The program loaded by CCS in core0 is loaded in core0 only L2RAM.

When you say "then loaded to slave cores" you mean the you load it with the CCS, or simple you "run" it by writing magical address and generating IPC interrupts?

To have one executable shared between cores the easy way is to use MCSM for shared resources and L2RAM for private ones (as stack). In the linker option and command file:
1. place all const section in MCSM (physical address is the same for every core)
2. place all data sections (stack, bss, far, fardata, sysmem) in L2RAM (same logical address, different physical memory)
3. If you have shared data, place all shared data in special section in MCSM
4. Link as ROM autoinitialization

0 Giovambattista Astorino over 8 years ago in reply to Alberto Chessa

Intellectual 290 points

I mean that simple I "run it by writing magical address and generating IPC interrupts". This is the .cmd i use:

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/project.7z

Everything now is in the MSMCRAM but it still doesn't work

0 Alberto Chessa over 8 years ago in reply to Giovambattista Astorino

Mastermind 6670 points

Hi,

The per-core private data shall be placed in per-core private RAM. By placing everything in MCSM, the per-core data sections overlaps.

For instance, since ".stack" in in MCSM and so implicitly shared, when core-N use the stack, it corrupts the stack used by other cores.

Something like:

SECTIONS
{
    //Shared
	.text	> MSMCSRAM
	.switch > MSMCSRAM
	.const > MSMCSRAM
	.cinit > MSMCSRAM    //ROM autoinit

    //Private
	.platform_lib > L2RAM    //not sure about this. I don't use platform lib
	.neardata > L2RAM
	.bss > L2RAM
	.far > L2RAM
	.fardata > L2RAM
	.cio > L2RAM
	.stack > L2RAM
	.sysmem > L2RAM
}

0 Giovambattista Astorino over 8 years ago in reply to Alberto Chessa

Intellectual 290 points

I moved some section to the DDR3 and now it works. Thanks a lot for your support

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TMS320C6678: Binary deployment at runtime