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TMS320C6657: How to test ECC functionality in DDR3 space

RandyP
Guru* 84110 points

Part Number: TMS320C6657

Can you point me, please, to a GEL or C test that will help us validate that the 36-bit ECC interface is working correctly? A customer has managed to setup the DDR3 so it is functionally working, but it does not see easy to figure out a way to generate an ECC error to validate correction and detection and interrupts and status bits.

I found a reference to one for Keystone 2 in MCSDK UG Chapter Exploring, but that appears to work from U-boot and therefore from the ARM in K2, but we are working with K1 C6657.

Regards,
RandyP

  • 0
    TI__Guru 65405 points
    Hi Randy,

    I've forwarded this to the c66x SW experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0
    TI__Guru** 116870 points
    Randy,

    I am checking internally on this request and will get back to you as soon as I find any relevant code to share with you.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    TI__Mastermind 46460 points

    Randy,

    There is no way to directly write to or read from the ECC bits.  You can only validate correct operation when it is all setup and functional.  Be sure to have the customer write and read the ECC protected region using aligned 32-bit accesses.

    All ECC protected memory must be written prior to being read.  This write initializes the contents of the ECC memory.

    I believe you can simulate an ECC error for testing by:

    1. DDR3 Controller and PHY initialization, including leveling
    2. Enable ECC and write to all ECC protested space
    3. Disable ECC
    4. Toggle a single bit in a single 32-bit word
    5. Enable ECC
    6. Read the previously altered location - an ECC error should be detected (and corrected)

    Tom