AM3703: GPIO not going to OFF state

Augustine Miu

Part Number: AM3703
Other Parts Discussed in Thread: OMAP3503, SYSCONFIG, CCSTUDIO

Hi,

We have a GPIO (GPIO96) that's configured to change state during OFF mode to indicates that the processor is fully off. This is fully working for OMAP3503. However, we migrate from OMAP3503 to AM3703 processor and the AM37 processor behave differently than the OMAP35 processor. Basically, the GPIO will drive to the proper state during the first suspend (OFF mode). Any subsequent suspend will not drive the pin to the OFF state.

I checked all the PM_PREPWSTST_x and every register indicates that the domain is OFF. Also, the SYS_OFF_MODE pin behaves the same way.

Can you suggest what could be the possible cause for this?

The following is the register dump before and after suspend.

"PRE-SUSPEND PRCM REGISTER SNAPSHOT" , , , ,
"----------------------------------" , , , ,
"IVA2_CM:" , , , ,
"CM_FCLKEN_IVA2 0x00000000" , , , ,
"CM_CLKEN_PLL_IVA2 0x0000021f" , , , ,
"CM_IDLEST_IVA2 0x00000001" , , , ,
"CM_IDLEST_PLL_IVA2 0x00000000" , , , ,
"CM_AUTOIDLE_PLL_IVA2 0x00000001" , , , ,
"CM_CLKSEL1_PLL_IVA2 0x000d142f" , , , ,
"CM_CLKSEL2_PLL_IVA2 0x00000001" , , , ,
"CM_CLKSTCTRL_IVA2 0x00000003" , , , ,
"CM_CLKSTST_IVA2 0x00000000" , , , ,
"OCP_System_Reg_CM:" , , , ,
"CM_REVISION 0x00000010" , , , ,
"CM_SYSCONFIG 0x00000001" , , , ,
"MPU_CM:" , , , ,
"CM_CLKEN_PLL_MPU 0x0000021f" , , , ,
"CM_IDLEST_MPU 0x00000000" , , , ,
"CM_IDLEST_PLL_MPU 0x00000001" , , , ,
"CM_AUTOIDLE_PLL_MPU 0x00000001" , , , ,
"CM_CLKSEL1_PLL_MPU 0x0012ee17" , , , ,
"CM_CLKSEL2_PLL_MPU 0x00000001" , , , ,
"CM_CLKSTCTRL_MPU 0x00000003" , , , ,
"CM_CLKSTST_MPU 0x00000001" , , , ,
"CORE_CM:" , , , ,
"CM_FCLKEN1_CORE 0x00000000" , , , ,
"CM_FCLKEN3_CORE 0x00000000" , , , ,
"CM_ICLKEN1_CORE 0x0000004a" , , , ,
"CM_ICLKEN2_CORE 0x00000000" , , , ,
"CM_ICLKEN3_CORE 0x00000000" , , , ,
"CM_IDLEST1_CORE 0xffffffbd" , , , ,
"CM_IDLEST2_CORE 0x0000001f" , , , ,
"CM_IDLEST3_CORE 0x0000000d" , , , ,
"CM_AUTOIDLE1_CORE 0x433ffe50" , , , ,
"CM_AUTOIDLE2_CORE 0x00000000" , , , ,
"CM_AUTOIDLE3_CORE 0x00000000" , , , ,
"CM_CLKSEL_CORE 0x0000148a" , , , ,
"CM_CLKSTCTRL_CORE 0x0000003f" , , , ,
"CM_CLKSTST_CORE 0x00000003" , , , ,
"SGX_CM:" , , , ,
"CM_FCLKEN_SGX 0x00000000" , , , ,
"CM_ICLKEN_SGX 0x00000000" , , , ,
"CM_IDLEST_SGX 0x00000000" , , , ,
"CM_CLKSEL_SGX 0x00000000" , , , ,
"CM_SLEEPDEP_SGX 0x00000000" , , , ,
"CM_CLKSTCTRL_SGX 0x00000000" , , , ,
"CM_CLKSTST_SGX 0x00000000" , , , ,
"WKUP_CM:" , , , ,
"CM_FCLKEN_WKUP 0x00000000" , , , ,
"CM_ICLKEN_WKUP 0x00000000" , , , ,
"CM_IDLEST_WKUP 0x000002ff" , , , ,
"CM_AUTOIDLE_WKUP 0x0000023f" , , , ,
"CM_CLKSEL_WKUP 0x00000014" , , , ,
"Clock_Control_Reg_CM:" , , , ,
"CM_CLKEN_PLL 0xc01f101f" , , , ,
"CM_CLKEN2_PLL 0x0000001f" , , , ,
"CM_IDLEST_CKGEN 0x00000001" , , , ,
"CM_IDLEST2_CKGEN 0x00000000" , , , ,
"CM_AUTOIDLE_PLL 0x00000009" , , , ,
"CM_AUTOIDLE2_PLL 0x00000001" , , , ,
"CM_CLKSEL1_PLL 0x09f41700" , , , ,
"CM_CLKSEL2_PLL 0x04421c0b" , , , ,
"CM_CLKSEL3_PLL 0x00000009" , , , ,
"CM_CLKSEL4_PLL 0x00003200" , , , ,
"CM_CLKSEL5_PLL 0x00000008" , , , ,
"CM_CLKOUT_CTRL 0x00000003" , , , ,
"DSS_CM:" , , , ,
"CM_FCLKEN_DSS 0x00000000" , , , ,
"CM_ICLKEN_DSS 0x00000000" , , , ,
"CM_IDLEST_DSS 0x00000003" , , , ,
"CM_AUTOIDLE_DSS 0x00000001" , , , ,
"CM_CLKSEL_DSS 0x00001005" , , , ,
"CM_SLEEPDEP_DSS 0x00000000" , , , ,
"CM_CLKSTCTRL_DSS 0x00000003" , , , ,
"CM_CLKSTST_DSS 0x00000000" , , , ,
"CAM_CM:" , , , ,
"CM_FCLKEN_CAM 0x00000000" , , , ,
"CM_ICLKEN_CAM 0x00000000" , , , ,
"CM_IDLEST_CAM 0x00000001" , , , ,
"CM_AUTOIDLE_CAM 0x00000000" , , , ,
"CM_CLKSEL_CAM 0x00000004" , , , ,
"CM_SLEEPDEP_CAM 0x00000000" , , , ,
"CM_CLKSTCTRL_CAM 0x00000003" , , , ,
"CM_CLKSTST_CAM 0x00000000" , , , ,
"PER_CM:" , , , ,
"CM_FCLKEN_PER 0x00000000" , , , ,
"CM_ICLKEN_PER 0x00000000" , , , ,
"CM_IDLEST_PER 0x0007ffff" , , , ,
"CM_AUTOIDLE_PER 0x0003e869" , , , ,
"CM_CLKSEL_PER 0x0000000c" , , , ,
"CM_SLEEPDEP_PER 0x00000002" , , , ,
"CM_CLKSTCTRL_PER 0x00000003" , , , ,
"CM_CLKSTST_PER 0x00000001" , , , ,
"EMU_CM:" , , , ,
"CM_CLKSEL1_EMU 0x03020a50" , , , ,
"CM_CLKSTCTRL_EMU 0x00000003" , , , ,
"CM_CLKSTST_EMU 0x00000000" , , , ,
"CM_CLKSEL2_EMU 0x00000000" , , , ,
"CM_CLKSEL3_EMU 0x00000000" , , , ,
"Global_Reg_CM:" , , , ,
"CM_POLCTRL 0x00000000" , , , ,
"NEON_CM:" , , , ,
"CM_IDLEST_NEON 0x00000000" , , , ,
"CM_CLKSTCTRL_NEON 0x00000003" , , , ,
"USBHOST_CM:" , , , ,
"CM_FCLKEN_USBHOST 0x00000000" , , , ,
"CM_ICLKEN_USBHOST 0x00000000" , , , ,
"CM_IDLEST_USBHOST 0x00000003" , , , ,
"CM_AUTOIDLE_USBHOST 0x00000001" , , , ,
"CM_SLEEPDEP_USBHOST 0x00000000" , , , ,
"CM_CLKSTCTRL_USBHOST 0x00000003" , , , ,
"CM_CLKSTST_USBHOST 0x00000000" , , , ,
"IVA2_PRM:" , , , ,
"RM_RSTCTRL_IVA2 0x00000007" , , , ,
"RM_RSTST_IVA2 0x00000000" , , , ,
"PM_WKDEP_IVA2 0x00000000" , , , ,
"PM_PWSTCTRL_IVA2 0x00ff0f00" , , , ,
"PM_PWSTST_IVA2 0x00000000" , , , ,
"PM_PREPWSTST_IVA2 0x00000000" , , , ,
"PRM_IRQSTATUS_IVA2 0x00000002" , , , ,
"PRM_IRQENABLE_IVA2 0x00000000" , , , ,
"OCP_System_Reg_PRM:" , , , ,
"PRM_REVISION 0x00000010" , , , ,
"PRM_SYSCONFIG 0x00000001" , , , ,
"PRM_IRQSTATUS_MPU 0x08000010" , , , ,
"PRM_IRQENABLE_MPU 0x01c926a0" , , , ,
"MPU_PRM:" , , , ,
"RM_RSTST_MPU 0x00000000" , , , ,
"PM_WKDEP_MPU 0x00000000" , , , ,
"PM_EVGENCTRL_MPU 0x00000012" , , , ,
"PM_EVGENONTIM_MPU 0x00000000" , , , ,
"PM_EVGENOFFTIM_MPU 0x00000000" , , , ,
"PM_PWSTCTRL_MPU 0x00030104" , , , ,
"PM_PWSTST_MPU 0x000000c7" , , , ,
"PM_PREPWSTST_MPU 0x000000c7" , , , ,
"CORE_PRM:" , , , ,
"RM_RSTST_CORE 0x00000000" , , , ,
"PM_WKEN1_CORE 0x00000000" , , , ,
"PM_MPUGRPSEL1_CORE 0xc33ffe18" , , , ,
"PM_IVA2GRPSEL1_CORE 0xc33ffe18" , , , ,
"PM_WKST1_CORE 0x00000000" , , , ,
"PM_WKST3_CORE 0x00000000" , , , ,
"PM_PWSTCTRL_CORE 0x000f0300" , , , ,
"PM_PWSTST_CORE 0x000000f7" , , , ,
"PM_PREPWSTST_CORE 0x000000f7" , , , ,
"PM_WKEN3_CORE 0x00000000" , , , ,
"PM_IVA2GRPSEL3_CORE 0x00000004" , , , ,
"PM_MPUGRPSEL3_CORE 0x00000004" , , , ,
"SGX_PRM:" , , , ,
"RM_RSTST_SGX 0x00000000" , , , ,
"PM_WKDEP_SGX 0x00000000" , , , ,
"PM_PWSTCTRL_SGX 0x00000000" , , , ,
"PM_PWSTST_SGX 0x00000000" , , , ,
"PM_PREPWSTST_SGX 0x00000000" , , , ,
"WKUP_PRM:" , , , ,
"PM_WKEN_WKUP 0x0000010a" , , , ,
"PM_MPUGRPSEL_WKUP 0x0000010a" , , , ,
"PM_IVA2GRPSEL_WKUP 0x00000000" , , , ,
"PM_WKST_WKUP 0x00000000" , , , ,
"Clock_Control_Reg_PRM:" , , , ,
"PRM_CLKSEL 0x00000002" , , , ,
"PRM_CLKOUT_CTRL 0x00000000" , , , ,
"DSS_PRM:" , , , ,
"RM_RSTST_DSS 0x0000000c" , , , ,
"PM_WKEN_DSS 0x00000000" , , , ,
"PM_WKDEP_DSS 0x00000000" , , , ,
"PM_PWSTCTRL_DSS 0x00030104" , , , ,
"PM_PWSTST_DSS 0x00000000" , , , ,
"PM_PREPWSTST_DSS 0x00000000" , , , ,
"CAM_PRM:" , , , ,
"RM_RSTST_CAM 0x00000000" , , , ,
"PM_WKDEP_CAM 0x00000000" , , , ,
"PM_PWSTCTRL_CAM 0x00030104" , , , ,
"PM_PWSTST_CAM 0x00000000" , , , ,
"PM_PREPWSTST_CAM 0x00000000" , , , ,
"PER_PRM:" , , , ,
"RM_RSTST_PER 0x00000000" , , , ,
"PM_WKEN_PER 0x0003e000" , , , ,
"PM_MPUGRPSEL_PER 0x0003efff" , , , ,
"PM_IVA2GRPSEL_PER 0x0007efff" , , , ,
"PM_WKST_PER 0x00000000" , , , ,
"PM_WKDEP_PER 0x00000012" , , , ,
"PM_PWSTCTRL_PER 0x00030104" , , , ,
"PM_PWSTST_PER 0x00000007" , , , ,
"PM_PREPWSTST_PER 0x00000007" , , , ,
"EMU_PRM:" , , , ,
"RM_RSTST_EMU 0x00000000" , , , ,
"PM_PWSTST_EMU 0x00000000" , , , ,
"Global_Reg_PRM:" , , , ,
"PRM_VC_SMPS_SA 0x00120012" , , , ,
"PRM_VC_SMPS_VOL_RA 0x00010000" , , , ,
"PRM_VC_SMPS_CMD_RA 0x00000000" , , , ,
"PRM_VC_CMD_VAL_0 0x28282000" , , , ,
"PRM_VC_CMD_VAL_1 0x2c202000" , , , ,
"PRM_VC_CH_CONF 0x00170000" , , , ,
"PRM_VC_I2C_CFG 0x00000005" , , , ,
"PRM_VC_BYPASS_VAL 0x00000000" , , , ,
"PRM_RSTCTRL 0x00000000" , , , ,
"PRM_RSTTIME 0x00001006" , , , ,
"PRM_RSTST 0x00000000" , , , ,
"PRM_VOLTCTRL 0x0000000c" , , , ,
"PRM_SRAM_PCHARGE 0x00000050" , , , ,
"PRM_CLKSRC_CTRL 0x00000050" , , , ,
"PRM_OBS 0x00000000" , , , ,
"PRM_VOLTSETUP1 0x01120112" , , , ,
"PRM_VOLTOFFSET 0x00000000" , , , ,
"PRM_CLKSETUP 0x000000a0" , , , ,
"PRM_POLCTRL 0x00000002" , , , ,
"PRM_VOLTSETUP2 0x00000000" , , , ,
"NEON_PRM:" , , , ,
"RM_RSTST_NEON 0x00000000" , , , ,
"PM_WKDEP_NEON 0x00000002" , , , ,
"PM_PWSTCTRL_NEON 0x00000004" , , , ,
"PM_PWSTST_NEON 0x00000003" , , , ,
"PM_PREPWSTST_NEON 0x00000003" , , , ,
"USBHOST_PRM:" , , , ,
"RM_RSTST_USBHOST 0x00000000" , , , ,
"PM_WKEN_USBHOST 0x00000000" , , , ,
"PM_MPUGRPSEL_USBHOST 0x00000000" , , , ,
"PM_IVA2GRPSEL_USBHOST 0x00000001" , , , ,
"PM_WKST_USBHOST 0x00000000" , , , ,
"PM_WKDEP_USBHOST 0x00000017" , , , ,
"PM_PWSTCTRL_USBHOST 0x00030104" , , , ,
"PM_PWSTST_USBHOST 0x00000000" , , , ,
"PM_PREPWSTST_USBHOST 0x00000000" , , , ,
"INTCPS_SYSCONFIG 0x00000000" , , , ,
"INTCPS_IDLE 0x00000001" , , , ,
"INTCPS_ITR0 0x00000002" , , , ,
"INTCPS_ITR1 0x00000000" , , , ,
"INTCPS_ITR2 0x01000800" , , , ,
"INTCPS_MIR0 0xdfffffff" , , , ,
"INTCPS_MIR1 0xffffffff" , , , ,
"INTCPS_MIR2 0xffffffff" , , , ,
"INTCPS_PENDING_IRQ0 0x00000000" , , , ,
"INTCPS_PENDING_IRQ1 0x00000000" , , , ,
"INTCPS_PENDING_IRQ2 0x00000000" , , , ,
"INTCPS_PENDING_FIQ0 0x00000000" , , , ,
"INTCPS_PENDING_FIQ1 0x00000000" , , , ,
"INTCPS_PENDING_FIQ2 0x00000000" , , , ,

"POST-SUSPEND PRCM REGISTER SNAPSHOT" , , , ,
"-----------------------------------" , , , ,
"IVA2_CM:" , , , ,
"CM_FCLKEN_IVA2 0x00000000" , , , ,
"CM_CLKEN_PLL_IVA2 0x0000021f" , , , ,
"CM_IDLEST_IVA2 0x00000001" , , , ,
"CM_IDLEST_PLL_IVA2 0x00000000" , , , ,
"CM_AUTOIDLE_PLL_IVA2 0x00000001" , , , ,
"CM_CLKSEL1_PLL_IVA2 0x000d142f" , , , ,
"CM_CLKSEL2_PLL_IVA2 0x00000001" , , , ,
"CM_CLKSTCTRL_IVA2 0x00000003" , , , ,
"CM_CLKSTST_IVA2 0x00000000" , , , ,
"OCP_System_Reg_CM:" , , , ,
"CM_REVISION 0x00000010" , , , ,
"CM_SYSCONFIG 0x00000001" , , , ,
"MPU_CM:" , , , ,
"CM_CLKEN_PLL_MPU 0x0000021f" , , , ,
"CM_IDLEST_MPU 0x00000000" , , , ,
"CM_IDLEST_PLL_MPU 0x00000001" , , , ,
"CM_AUTOIDLE_PLL_MPU 0x00000001" , , , ,
"CM_CLKSEL1_PLL_MPU 0x0012ee17" , , , ,
"CM_CLKSEL2_PLL_MPU 0x00000001" , , , ,
"CM_CLKSTCTRL_MPU 0x00000003" , , , ,
"CM_CLKSTST_MPU 0x00000001" , , , ,
"CORE_CM:" , , , ,
"CM_FCLKEN1_CORE 0x00000000" , , , ,
"CM_FCLKEN3_CORE 0x00000000" , , , ,
"CM_ICLKEN1_CORE 0x0000004a" , , , ,
"CM_ICLKEN2_CORE 0x00000000" , , , ,
"CM_ICLKEN3_CORE 0x00000000" , , , ,
"CM_IDLEST1_CORE 0xffffffbd" , , , ,
"CM_IDLEST2_CORE 0x0000001f" , , , ,
"CM_IDLEST3_CORE 0x0000000d" , , , ,
"CM_AUTOIDLE1_CORE 0x433ffe50" , , , ,
"CM_AUTOIDLE2_CORE 0x00000000" , , , ,
"CM_AUTOIDLE3_CORE 0x00000000" , , , ,
"CM_CLKSEL_CORE 0x0000148a" , , , ,
"CM_CLKSTCTRL_CORE 0x0000003f" , , , ,
"CM_CLKSTST_CORE 0x00000003" , , , ,
"SGX_CM:" , , , ,
"CM_FCLKEN_SGX 0x00000000" , , , ,
"CM_ICLKEN_SGX 0x00000000" , , , ,
"CM_IDLEST_SGX 0x00000000" , , , ,
"CM_CLKSEL_SGX 0x00000000" , , , ,
"CM_SLEEPDEP_SGX 0x00000000" , , , ,
"CM_CLKSTCTRL_SGX 0x00000000" , , , ,
"CM_CLKSTST_SGX 0x00000000" , , , ,
"WKUP_CM:" , , , ,
"CM_FCLKEN_WKUP 0x00000001" , , , ,
"CM_ICLKEN_WKUP 0x0000000d" , , , ,
"CM_IDLEST_WKUP 0x000002f2" , , , ,
"CM_AUTOIDLE_WKUP 0x0000023f" , , , ,
"CM_CLKSEL_WKUP 0x00000014" , , , ,
"Clock_Control_Reg_CM:" , , , ,
"CM_CLKEN_PLL 0xc01f101f" , , , ,
"CM_CLKEN2_PLL 0x0000001f" , , , ,
"CM_IDLEST_CKGEN 0x00000001" , , , ,
"CM_IDLEST2_CKGEN 0x00000000" , , , ,
"CM_AUTOIDLE_PLL 0x00000009" , , , ,
"CM_AUTOIDLE2_PLL 0x00000001" , , , ,
"CM_CLKSEL1_PLL 0x09f41700" , , , ,
"CM_CLKSEL2_PLL 0x04421c0b" , , , ,
"CM_CLKSEL3_PLL 0x00000009" , , , ,
"CM_CLKSEL4_PLL 0x00003200" , , , ,
"CM_CLKSEL5_PLL 0x00000008" , , , ,
"CM_CLKOUT_CTRL 0x00000003" , , , ,
"DSS_CM:" , , , ,
"CM_FCLKEN_DSS 0x00000000" , , , ,
"CM_ICLKEN_DSS 0x00000000" , , , ,
"CM_IDLEST_DSS 0x00000003" , , , ,
"CM_AUTOIDLE_DSS 0x00000000" , , , ,
"CM_CLKSEL_DSS 0x00000405" , , , ,
"CM_SLEEPDEP_DSS 0x00000000" , , , ,
"CM_CLKSTCTRL_DSS 0x00000003" , , , ,
"CM_CLKSTST_DSS 0x00000000" , , , ,
"CAM_CM:" , , , ,
"CM_FCLKEN_CAM 0x00000000" , , , ,
"CM_ICLKEN_CAM 0x00000000" , , , ,
"CM_IDLEST_CAM 0x00000001" , , , ,
"CM_AUTOIDLE_CAM 0x00000000" , , , ,
"CM_CLKSEL_CAM 0x00000004" , , , ,
"CM_SLEEPDEP_CAM 0x00000000" , , , ,
"CM_CLKSTCTRL_CAM 0x00000003" , , , ,
"CM_CLKSTST_CAM 0x00000000" , , , ,
"PER_CM:" , , , ,
"CM_FCLKEN_PER 0x00000008" , , , ,
"CM_ICLKEN_PER 0x0003e008" , , , ,
"CM_IDLEST_PER 0x00041ff7" , , , ,
"CM_AUTOIDLE_PER 0x0003e008" , , , ,
"CM_CLKSEL_PER 0x00000000" , , , ,
"CM_SLEEPDEP_PER 0x00000002" , , , ,
"CM_CLKSTCTRL_PER 0x00000003" , , , ,
"CM_CLKSTST_PER 0x00000001" , , , ,
"EMU_CM:" , , , ,
"CM_CLKSEL1_EMU 0x03020a50" , , , ,
"CM_CLKSTCTRL_EMU 0x00000003" , , , ,
"CM_CLKSTST_EMU 0x00000000" , , , ,
"CM_CLKSEL2_EMU 0x00000000" , , , ,
"CM_CLKSEL3_EMU 0x00000000" , , , ,
"Global_Reg_CM:" , , , ,
"CM_POLCTRL 0x00000000" , , , ,
"NEON_CM:" , , , ,
"CM_IDLEST_NEON 0x00000000" , , , ,
"CM_CLKSTCTRL_NEON 0x00000003" , , , ,
"USBHOST_CM:" , , , ,
"CM_FCLKEN_USBHOST 0x00000000" , , , ,
"CM_ICLKEN_USBHOST 0x00000000" , , , ,
"CM_IDLEST_USBHOST 0x00000003" , , , ,
"CM_AUTOIDLE_USBHOST 0x00000000" , , , ,
"CM_SLEEPDEP_USBHOST 0x00000000" , , , ,
"CM_CLKSTCTRL_USBHOST 0x00000003" , , , ,
"CM_CLKSTST_USBHOST 0x00000000" , , , ,
"IVA2_PRM:" , , , ,
"RM_RSTCTRL_IVA2 0x00000007" , , , ,
"RM_RSTST_IVA2 0x00000000" , , , ,
"PM_WKDEP_IVA2 0x00000000" , , , ,
"PM_PWSTCTRL_IVA2 0x00ff0f00" , , , ,
"PM_PWSTST_IVA2 0x00000000" , , , ,
"PM_PREPWSTST_IVA2 0x00000000" , , , ,
"PRM_IRQSTATUS_IVA2 0x00000002" , , , ,
"PRM_IRQENABLE_IVA2 0x00000000" , , , ,
"OCP_System_Reg_PRM:" , , , ,
"PRM_REVISION 0x00000010" , , , ,
"PRM_SYSCONFIG 0x00000001" , , , ,
"PRM_IRQSTATUS_MPU 0x08000211" , , , ,
"PRM_IRQENABLE_MPU 0x01c926a0" , , , ,
"MPU_PRM:" , , , ,
"RM_RSTST_MPU 0x00000000" , , , ,
"PM_WKDEP_MPU 0x00000000" , , , ,
"PM_EVGENCTRL_MPU 0x00000012" , , , ,
"PM_EVGENONTIM_MPU 0x00000000" , , , ,
"PM_EVGENOFFTIM_MPU 0x00000000" , , , ,
"PM_PWSTCTRL_MPU 0x00030105" , , , ,
"PM_PWSTST_MPU 0x000000c7" , , , ,
"PM_PREPWSTST_MPU 0x00000000" , , , ,
"CORE_PRM:" , , , ,
"RM_RSTST_CORE 0x00000000" , , , ,
"PM_WKEN1_CORE 0x00000000" , , , ,
"PM_MPUGRPSEL1_CORE 0xc33ffe18" , , , ,
"PM_IVA2GRPSEL1_CORE 0xc33ffe18" , , , ,
"PM_WKST1_CORE 0x00000000" , , , ,
"PM_WKST3_CORE 0x00000000" , , , ,
"PM_PWSTCTRL_CORE 0x000f0301" , , , ,
"PM_PWSTST_CORE 0x000000f7" , , , ,
"PM_PREPWSTST_CORE 0x00000000" , , , ,
"PM_WKEN3_CORE 0x00000000" , , , ,
"PM_IVA2GRPSEL3_CORE 0x00000004" , , , ,
"PM_MPUGRPSEL3_CORE 0x00000004" , , , ,
"SGX_PRM:" , , , ,
"RM_RSTST_SGX 0x00000000" , , , ,
"PM_WKDEP_SGX 0x00000000" , , , ,
"PM_PWSTCTRL_SGX 0x00000000" , , , ,
"PM_PWSTST_SGX 0x00000000" , , , ,
"PM_PREPWSTST_SGX 0x00000000" , , , ,
"WKUP_PRM:" , , , ,
"PM_WKEN_WKUP 0x0000000b" , , , ,
"PM_MPUGRPSEL_WKUP 0x0000010a" , , , ,
"PM_IVA2GRPSEL_WKUP 0x00000000" , , , ,
"PM_WKST_WKUP 0x00000108" , , , ,
"Clock_Control_Reg_PRM:" , , , ,
"PRM_CLKSEL 0x00000002" , , , ,
"PRM_CLKOUT_CTRL 0x00000000" , , , ,
"DSS_PRM:" , , , ,
"RM_RSTST_DSS 0x00000000" , , , ,
"PM_WKEN_DSS 0x00000000" , , , ,
"PM_WKDEP_DSS 0x00000000" , , , ,
"PM_PWSTCTRL_DSS 0x00030104" , , , ,
"PM_PWSTST_DSS 0x00000000" , , , ,
"PM_PREPWSTST_DSS 0x00000000" , , , ,
"CAM_PRM:" , , , ,
"RM_RSTST_CAM 0x00000000" , , , ,
"PM_WKDEP_CAM 0x00000000" , , , ,
"PM_PWSTCTRL_CAM 0x00030104" , , , ,
"PM_PWSTST_CAM 0x00000000" , , , ,
"PM_PREPWSTST_CAM 0x00000000" , , , ,
"PER_PRM:" , , , ,
"RM_RSTST_PER 0x00000000" , , , ,
"PM_WKEN_PER 0x0003e008" , , , ,
"PM_MPUGRPSEL_PER 0x0003efff" , , , ,
"PM_IVA2GRPSEL_PER 0x0007efff" , , , ,
"PM_WKST_PER 0x00000000" , , , ,
"PM_WKDEP_PER 0x00000002" , , , ,
"PM_PWSTCTRL_PER 0x00030105" , , , ,
"PM_PWSTST_PER 0x00000007" , , , ,
"PM_PREPWSTST_PER 0x00000000" , , , ,
"EMU_PRM:" , , , ,
"RM_RSTST_EMU 0x00000000" , , , ,
"PM_PWSTST_EMU 0x00000000" , , , ,
"Global_Reg_PRM:" , , , ,
"PRM_VC_SMPS_SA 0x00120012" , , , ,
"PRM_VC_SMPS_VOL_RA 0x00010000" , , , ,
"PRM_VC_SMPS_CMD_RA 0x00000000" , , , ,
"PRM_VC_CMD_VAL_0 0x28282000" , , , ,
"PRM_VC_CMD_VAL_1 0x2c202000" , , , ,
"PRM_VC_CH_CONF 0x00170000" , , , ,
"PRM_VC_I2C_CFG 0x00000005" , , , ,
"PRM_VC_BYPASS_VAL 0x00000000" , , , ,
"PRM_RSTCTRL 0x00000000" , , , ,
"PRM_RSTTIME 0x00001006" , , , ,
"PRM_RSTST 0x00000000" , , , ,
"PRM_VOLTCTRL 0x0000000c" , , , ,
"PRM_SRAM_PCHARGE 0x00000050" , , , ,
"PRM_CLKSRC_CTRL 0x00000050" , , , ,
"PRM_OBS 0x00000000" , , , ,
"PRM_VOLTSETUP1 0x01120112" , , , ,
"PRM_VOLTOFFSET 0x00000000" , , , ,
"PRM_CLKSETUP 0x000000a0" , , , ,
"PRM_POLCTRL 0x00000002" , , , ,
"PRM_VOLTSETUP2 0x00000000" , , , ,
"NEON_PRM:" , , , ,
"RM_RSTST_NEON 0x00000000" , , , ,
"PM_WKDEP_NEON 0x00000002" , , , ,
"PM_PWSTCTRL_NEON 0x00000005" , , , ,
"PM_PWSTST_NEON 0x00000003" , , , ,
"PM_PREPWSTST_NEON 0x00000000" , , , ,
"USBHOST_PRM:" , , , ,
"RM_RSTST_USBHOST 0x00000000" , , , ,
"PM_WKEN_USBHOST 0x00000000" , , , ,
"PM_MPUGRPSEL_USBHOST 0x00000000" , , , ,
"PM_IVA2GRPSEL_USBHOST 0x00000001" , , , ,
"PM_WKST_USBHOST 0x00000000" , , , ,
"PM_WKDEP_USBHOST 0x00000017" , , , ,
"PM_PWSTCTRL_USBHOST 0x00030104" , , , ,
"PM_PWSTST_USBHOST 0x00000003" , , , ,
"PM_PREPWSTST_USBHOST 0x00000000" , , , ,
"INTCPS_SYSCONFIG 0x00000000" , , , ,
"INTCPS_IDLE 0x00000010" , , , ,
"INTCPS_ITR0 0x20000802" , , , ,
"INTCPS_ITR1 0x00000020" , , , ,
"INTCPS_ITR2 0x01000800" , , , ,
"INTCPS_MIR0 0x5dffe7ff" , , , ,
"INTCPS_MIR1 0xfffffdd8" , , , ,
"INTCPS_MIR2 0xbfb7dff5" , , , ,
"INTCPS_PENDING_IRQ0 0x20000800" , , , ,
"INTCPS_PENDING_IRQ1 0x00000020" , , , ,
"INTCPS_PENDING_IRQ2 0x00000000" , , , ,
"INTCPS_PENDING_FIQ0 0x00000000" , , , ,
"INTCPS_PENDING_FIQ1 0x00000000" , , , ,
"INTCPS_PENDING_FIQ2 0x00000000" , , , ,

Thanks

Augustine

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

The PM experts have been notified. They will respond here.

0 Pavel Botev over 8 years ago

TI__Guru**** 170625 points

Hi Augustine,

Do you use AM37x TI EVM or custom board? Do you use LINUXEZSDK-AM37X v06.00?

There are some silicon errata notes related to AM37x GPIO and OFF mode, make sure you are aligned with the workarounds:

www.ti.com/.../sprz318f.pdf

Usage Note 2.9 GPIO is Driving Random Values When Device Returns From OFF Mode
Advisory 1.45 GPIO Pad Spurious Transition (Glitch/Spike) During Wake Up Entering or Exiting System OFF Mode
Advisory 1.9 Inactive State Management: Impossible to Transition to OFF or RETENTION States
Advisory 1.107 Some Power Domains Cannot Go To OFF Mode After Warm Reset

See also the below document which listed difference between OMAP35x and AM37x:

processors.wiki.ti.com/.../OMAP35x_To_AM37x_Hardware_Migration_Guide

Regards,
Pavel

0 Augustine Miu over 8 years ago in reply to Pavel Botev

Prodigy 220 points

Hi Pavel,

Thanks for your response. We are using a custom board and it's running WinCE.

Please correct me if I am wrong, but I take a look at the Errata and I don't think they cause the problem that I experience.

Usage Note 2.9 GPIO is Driving Random Values When Device Returns From OFF Mode

Answer: This errata is for when the device return from OFF mode, but my problem is when the unit is going into OFF mode where the state is not driven properly.

Advisory 1.45 GPIO Pad Spurious Transition (Glitch/Spike) During Wake Up Entering or Exiting System OFF Mode

Answer: This errata indicates we might get a nanosecond glitch when the device is going to OFF state, but my problem is the GPIO will never goes to the OFF state. In addition, the pin is actually set to drive high during ON state and Low during OFF state. Base on the workaround, I should not observe this problem.

Advisory 1.9 Inactive State Management: Impossible to Transition to OFF or RETENTION States

Answer: Base on my register dump, I don't see any modules goes to INACTIVE state so I don't think this cause the issue.

Advisory 1.107 Some Power Domains Cannot Go To OFF Mode After Warm Reset

Answer: This seems to be a very specify case where I need to perform a warm reset while the device is transition to a different states. A warm reset is not triggered when I observe the problem.

Base on the PREPWSTST register, all the modules are in OFF state. Is there other registers that I can use to pin point where the potential problem is?

Thanks

Augustine

0 Pavel Botev over 8 years ago in reply to Augustine Miu

TI__Guru**** 170625 points

Augustine,

I am not familiar with WinCE, so I can advice only from device side.

In OFF mode, all power domains are powered off except the wake up domain VDD3. GPIO96 belongs to GPIO4 module, which is part of the PER power domain.

From what I understand, below is your use case (please confirm):

1. AM37x is active, PM_PWSTST_PER[1:0] POWERSTATEST = 0x7 (ON state), GPIO_96 pin output value is as expected (it is 1)

2. AM37x transition from active to off mode, PM_PWSTST_PER[1:0] POWERSTATEST = 0x0 (OFF state), PM_PREPWSTST_PER[1:0] LASTPOWERSTATEENTERED = 0x3 (domain was ON), GPIO_96 pin output value is as expected (it is 0)

3. AM37x transition from off to active mode, PM_PWSTST_PER[1:0] POWERSTATEST = 0x7 (ON state), PM_PREPWSTST_PER[1:0] LASTPOWERSTATEENTERED = 0x0 (domain was OFF), GPIO_96 pin output value is as expected (it is 1)

4. AM37x transition from active to off mode ---> from what I understand you observe the issue in this step, is that correct? And the issue is that you cannot enter off mode? Or you are able to enter off mode, but GPIO_96 pin output value is NOT as expected (it is still 1, instead of 0)?

See also if the below wiki pages will be in help:

processors.wiki.ti.com/.../DM37x_OFF_mode_PAD_configuration
processors.wiki.ti.com/.../DM37x_Schematic_Checklist
processors.wiki.ti.com/.../OMAP35x-AM37x-DM37x_with_TPS65073:_Design_In_Guide

Regards,
Pavel

0 Augustine Miu over 8 years ago in reply to Pavel Botev

Prodigy 220 points

Hi Pavel,

Thanks for the response and I understand you are not familiar with CE. However, I do want to get your help from device perspective.

Yes, your description is correct. My problem is at step 4 where GPIO_96 is still 1 in OFF mode. Base on register PM_PREPWSTST_PER[1:0] LASTPOWERSTATEENTERED, it seems to me the PER domain is OFF, which should drive GPIO_96 to 0 when it's OFF. However, what I observed is that GPIO_96 is still 1 (Also, please note that the SYS_OFF_MODE pin behaves the same way except it should be 0 during ON and 1 during OFF).

Base on the information I provided. Do you think the PER domain is in fact in OFF state and the problem is mostly caused by an errata? Or if GPIO_96 indicates that some of the domain is not fully OFF, is there any registers that I can check to narrow down the problem?

Thanks

Augustine

0 Pavel Botev over 8 years ago in reply to Augustine Miu

TI__Guru**** 170625 points

Augustine Miu said:
Yes, your description is correct. My problem is at step 4 where GPIO_96 is still 1 in OFF mode. Base on register PM_PREPWSTST_PER[1:0] LASTPOWERSTATEENTERED, it seems to me the PER domain is OFF, which should drive GPIO_96 to 0 when it's OFF. However, what I observed is that GPIO_96 is still 1 (Also, please note that the SYS_OFF_MODE pin behaves the same way except it should be 0 during ON and 1 during OFF).

First of all let we check if your device is really going into OFF mode in step 4.

sys_off_mode - output pin, requests the external power IC to switch the device voltage level according to the device power status. From what I understand you have the expected values on this pin, is that correct?

You can also monitor sys_clkout1 pin. sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be controlled by software or externally using sys_clkreq control. When the device is in the off state, the sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the device. The off state polarity of sys_clkout1 is programmable. See TRM section 3.5.3.5.3 External Output Clock1 (sys_clkout1) Control

When you enter into OFF mode (in step 4) you can attach JTAG debugger and check the PM_PREPWSTST_PER and PM_PWSTST_PER registers values are per expected.

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AM3703: GPIO not going to OFF state