Part Number: AM5728
Tool/software: Code Composer Studio
Hi,
I am working to implement an Ethernet protocol on the PRU. I am already able to send packets. I use the C Compiler from CSS7. I use the TI IDK with AM5728.
In order to send the packet, I push the data and CRC into the TX Fifo an then assert TX_ENABLE from the corresponding MII. I do not use „32-bit Data Push mode“.
Now my question:
When I am reading the TX-FIFO-level I see that it increases by 4, every time I use the 16 Bit Push command from R31 (and 2 if I use 8 Bit Push).
This register (PRUSS_MII_RT_TXFLV1) shows always the double amount of bytes I am loading into it.
As receiver I use a Linux Notebook and wireshark. The packet is received intact.
So how is the TX-FIFO-level interpreted? Is it in Nibbles? I know the TRM says its bytes. Or is there another source of error?
Additionilly it would be interesting to use „32-bit Data Push mode“ in C. The problem here is how to guarantee that 4 or 2 or 1 Byte is written in one cycle to R30.
My initialization sequence is:
MII_RT.GET_PRU_REG_BIT(TXCFG).TX_CLK_DELAY = 0x6;
MII_RT.GET_PRU_REG_BIT(TXCFG).TX_START_DELAY = 0x40;
MII_RT.GET_PRU_REG_BIT(TXCFG).TX_32_MODE_EN = 0x0;
MII_RT.GET_PRU_REG_BIT(TXCFG).TX_AUTO_SEQUENCE = 0x0;
MII_RT.GET_PRU_REG_BIT(TXCFG).TX_MUX_SEL = 0x1;
MII_RT.GET_PRU_REG_BIT(TXCFG).TX_BYTE_SWAP = 0x0;
MII_RT.GET_PRU_REG_BIT(TXCFG).TX_EN_MODE = 0x0;
MII_RT.GET_PRU_REG_BIT(TXCFG).TX_AUTO_PREAMBLE = 0x1;
To push data I use:
__R30 = data_16 | TXMASK;
__R31 = MII_TX_PUSH16;
with R31 in mii mode.
I checked the HW registers with CSS and XDS100.
Regards
Hermann
