I'm writing driver for LCDC LIDD mode display controller.
I've encountered problem with data transfer over I80 - 8 bit type I interface.
We use RGB565 16-bit pixel format.
When I write 16-bit color value:
regs->LIDD_CS0_DATA = color;
only lower 8 bits are written to the device, as a result writing 2 pixels to the register updates one pixel in the GRAM with malformed color:
- upper byte of the pixel in GRAM is lower byte of first pixel
- lower byte of the pixel in GRAM is lower byte of second pixel.
So the easy workaround in the code for direct write access is to provide two write operations:
regs->LIDD_CS0_DATA = (color >> 8) & 0xFF;
regs->LIDD_CS0_DATA = color & 0xFF;
The problem category arises to critical when we use DMA transfer.
picture_data = { 0xFF, 0x00, 0xFF, 0x00}
regs->LCDDMA_FB0_BASE
= picture_data
regs->LCDDMA_FB0_CEILING = picture_data + 4 /* 2 x 16 bit
wide pixel */
In result DMA does the same as direct access write, it updates not four bytes of GRAM but two and the pixel data is malformed.
GRAM DATA = { 0x00, 0x00 }
The only and unacceptable workaround is to prepare wired pixel format that encapsulates 16 bit picture like:
picture_data = { 0xDD/*ignored*/, 0xFF, 0xDD, 0x00, 0xDD, 0xFF, 0xDD, 0x00}
And transfer doulble sized array:
regs->LCDDMA_FB0_BASE = picture_data
regs->LCDDMA_FB0_CEILING =
picture_data + 8 /* 2 x wired
32 bit wide pixel */
Is this the way it works or we
missed something ?
I can't see any indication of this behavior in lcdc user
manual (TMS320C674x/OMAP-L1x).
What I can see is:
- Page 15. Table 3.
8080 Family: DATA[7:0] - Data Bus (16 bits always available)
- Page 40. Table 17.
15-0: DATA: 0-FFFFh:
Peripheral Device Data value. On writes this field is loaded into the CS0
peripheral device On
reads this field contains the
CS0 peripheral device's data.
There is nothing about multiple read/writes required according to different 8080 interface connected to the controller.
Can anyone put some more light on how it is implemented internaly ? Have we missed something ?
Best Regards,
Maciek
LCDC reg dump:
[04h] LCDC_CTRL = 00000000h
MODE = 0h
CLKDIV = 0h
[0Ch] LIDD_CTRL = 00000003h
LIDD_MODE =
3
LCD_LIDD_CTRL_ALEPOL_BIT = 0
LCD_LIDD_CTRL_RS_EN_POL_BIT =
0
LCD_LIDD_CTRL_WS_DIR_POL_BIT = 0
LCD_LIDD_CTRL_CS0_E0_POL_BIT =
0
LCD_LIDD_CTRL_CS1_E1_POL_BIT = 0
LCD_LIDD_CTRL_DMA_CS0_CS1_BIT =
0
LCD_LIDD_CTRL_DMA_ENABLE_BIT = 0
LCD_LIDD_CTRL_DONE_INT_EN_BIT =
0
[10h] LIDD_CS0_CONF = 0064020Ch
TA = 0
R_HOLD = 3
R_STROBE = 8
R_SU = 0
W_HOLD = 2
W_STROBE = 3
W_SU = 0
[1Ch] LIDD_CS1_CONF = 00000000h
[28h] RASTER_CTRL =
00000000h
[2Ch] RASTER_TIMING_0 = 00000000h
[30h] RASTER_TIMING_1 =
00000000h
[34h] RASTER_TIMING_2 = 00000000h
[38h] RASTER_SUBPANEL =
00000000h
[40h] LCDDMA_CTRL = 00000000h
FRAME_MODE = 0
BIGENDIAN = 0
EOF_INTEN = 0
BURST_SIZE = 0
TH_FIFO_READY = 0
