AM3358: Board main clock failure

Hi,

It's impossible to suggest anything without seeing the board schematics. Can you post this?

Hello Biser,

Please send me an email so I can share the schematic internally.

Got it, thanks.

I don't see anything wrong around the main oscillator. I have exactly the same crystal and RC values on a customer board I designed several years ago, and it has never shown this problem. I suggest you check the power supply sequencing and reset. Also check power supplies for excessive ripples.

Biser,
See customer response below:
We don’t see any power supply ripples, and we believe we are following the proper reset and sequencing of the power supplies.

We have been studying this problem for several weeks now. The issue appears in about 25% of our boards, and it may take several thousand power cycles until we see the issue. We are really scratching our heads trying to figure out what is going wrong.

Is there anything specific relating to the reset or power sequencing that would cause this failure on the internal oscillator?

You say they are power cycling the boards. What is the time from power-off to power-on? Could it be that it's too small and board capacitors cannot discharge fully?

Hi Biser,

Customer feedback below:

The discharge time between power cycles is 3 seconds. All of the power PMIC regulated rails that we’ve monitored are down in under 20ms. In the scope shots below we added 470uF of capacitance on SYS_5V to allow the PMIC to gracefully shut down using under voltage lockout when external power is removed. The extra capacitance holds SYS_5V up for an extended period of time but should have no influence on the AM3358. Our observations on timing are as follows:

1. 24V input power is pulled.(24VSW_OUT)

2. 5V into the PMIC decreases until it triggers the undervoltage lockout (UVLO) fault at 3.3V

3. 3V3B is running on VDD_5V, the input voltage to the PMIC which gets disconnected from the 470uF cap on SYS_5V and begins to drop. We believe it then gets held up backfed through 3V3A.

4. After 4-6ms deglitch time VDD_CORE is brought down by the PMIC.

5. 1 ms later 3V3A is turned off by the PMIC. This allows 3V3B to come down.

6. 3V3A gets backfed from VDDS (it tracks with RTC but we initially had it tied to 1V8 off LDO3 and it follows)

7. 7ms later to PMIC turns off VDD_RTC. 3V3A then drops along with it.

Thanks,

Antonio

Hi Antonio
As noted in the internal escalation thread, please have the customer engineering team review the following post to see if it helps and jives with issues they are seeing

e2e.ti.com/.../1732942

Regards
Mukul