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Linux/DM385: DM385 VOUT0 RGB888 output?

yuantong lu
Prodigy 175 points

Part Number: DM385

Tool/software: Linux

Hello Everyone,

How can I configure the VOUT0(DVO2) in RGB 888 video output ? Now,my device only G(reen) PINs and B(lue) Pins have output waveform， just R(ed) Pin none ! Then ,my outpu image is only have green and bue pixel.I configure the VOUT0 HD_VENC Register HD_VENC_D_cfg0 vps_write32(A000, 0x44013051); What can I do ?

  • 0
    TI__Guru**** 501045 points

    Hi Lu,

    It is possible to get RGB888 output on DVO2. the Bits [18:16] in this register should be set to 011'b to get RGB888 output. You are currently setting output to two channel, which is why red channel is not outputting anything. 

    Btw, are you using HDVPSS drivers to configure it?

    Rgds,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 175 points

    Hi Brijesh,

    Thank you for reply!

    I refered to spruhi7a hdvpss.pdf ,and  the Bits [18:16] had been set to 011 , the red channel is still not outputting anything.

    Some of code modification refers to the link below

    Rgds,

    Lu

  • 0 in reply to yuantong lu
    TI__Guru**** 501045 points
    Can you check if PINMUX is set up for the red channel?
    Also please check if useEmbedded sync flag is set to 0?

    Regards,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Prodigy 175 points
    The PINMUX for VOUT[0] has been set ;
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AB8) = 0x1; /* vout0_fid_mux1 */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0ABC) = 0x1; /* vout0_clk */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AC0) = 0x1; /* vout0_hsync */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AC4) = 0x1; /* vout0_vsync */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AC8) = 0x1; /* vout0_avid */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0ACC) = 0x1; /* vout0_b_cb_c[2] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AD0) = 0x1; /* vout0_b_cb_c[3] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AD4) = 0x1; /* vout0_b_cb_c[4] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AD8) = 0x1; /* vout0_b_cb_c[5] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0ADC) = 0x1; /* vout0_b_cb_c[6] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AE0) = 0x1; /* vout0_b_cb_c[7] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AE4) = 0x1; /* vout0_b_cb_c[8] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AE8) = 0x1; /* vout0_b_cb_c[9] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AEC) = 0x1; /* vout0_g_y_yc[2] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AF0) = 0x1; /* vout0_g_y_yc[3] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AF4) = 0x1; /* vout0_g_y_yc[4] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AF8) = 0x1; /* vout0_g_y_yc[5] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AFC) = 0x1; /* vout0_g_y_yc[6] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B00) = 0x1; /* vout0_g_y_yc[7] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B04) = 0x1; /* vout0_g_y_yc[8] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B08) = 0x1; /* vout0_g_y_yc[9] */
    //red
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B0C) = 0x1; /* vout0_r_cr[2] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B10) = 0x1; /* vout0_r_cr[3] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B14) = 0x1; /* vout0_r_cr[4] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B18) = 0x1; /* vout0_r_cr[5] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B1C) = 0x1; /* vout0_r_cr[6] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B20) = 0x1; /* vout0_r_cr[7] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B24) = 0x1; /* vout0_r_cr[8] */
    REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B28) = 0x1; /* vout0_r_cr[9] */

    Sorry,I don't know how to set the useEmbedded sync flag.

    Regards,
    Lu
  • 0 in reply to yuantong lu
    TI__Guru**** 501045 points

    Hi Lu,

    Can you share complete VENC register settings? 

    If you set the output to Three channel discrete sync output, it should output even on Red channel. In fact, RGB output is tested in DVR-RDK for Sil9022a encoder. it is working fine. Are you using DVR-RDK? Can you run one of the usecase to see if it outputs on DVO2?

    Rgds,

    Brijesh 

  • 0 in reply to Brijesh Jadav
    Prodigy 175 points
    Hi Brijesh,
    Thanks for your help ! When I configure the VOUT0 HD_VENC Register HD_VENC_D_cfg0 vps_write32(A000, 0x44037033); the problem has been resolved.Thanks again!



    Best Regards,

    Lu