• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 98 subscribers
  • Views 1068 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2G02: DDR3 Layout, vias per trace for ADDR_CTRL

Andy Snawerdt
Intellectual 2700 points

Part Number: 66AK2G02

Hi team,

 

Based on K2G data sheet, Table 7-11, the maximum number of vias per trace for ADDR_CTRL routing group is 3 (See NO. CARS316).

The ADDR_CTRL topology makes it really hard to meet this requirement. For example, the trace of DDR_CK has 7 vias on reference design K2G EVM board. Those 7 vias are for: K2G processor, 1st DDR device( for ECC), 2nd DDR device, 3rd DDR device, 4th DDR device, 5th DDR device and termination resister.

As long as we have multiple DDR devices it is impossible to fulfill this requirement. The note(1) in the bottom of table allows us to extend the number of vias but need to have detail signal integrity analysis to confirm that.

 

Therefore,

How can we limit the number of vias to 3  for traces in ADDR_CTRL group with three 16-bit DDR3L devices(one is for ECC)?

 

 

Thanks!

  • 0
    TI__Guru**** 161600 points
    Hi Andy,

    I've notified the factory team. Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0
    TI__Mastermind 42545 points

    Hi Andy,

    I did check and you are right that the number of vias on the address/command lines are either 6 or 7 on the K2G EVM, however, we did extensive simulation on that design to ensure that signal integrity would be maintained, as suggested in the footnote. Regardless I think that 3 is restrictive and I will discuss this with the data sheet team. Often these tables include values that are the absolute maximum we believe will with work if the customer hasn't done any simulation. Since this interface is not very forgiving of layout problems, those maximums are set aggressively low. 

    Regards,

    Bill

  • 0 in reply to Bill Taboada
    TI__Intellectual 2700 points
    Hi Bill,

    Thanks for the response.

    Keep me posted on what the data sheet team says.

    Ultimately I would just like to know how many vias I can place without having to do extensive simulation to verify signal integrity, and if the number really is 3, the question comes back to how we can hit that number for traces in ADDR_CTRL group with three 16-bit DDR3L devices.

    Thanks for your help.

    -Andy
  • 0 in reply to Andy Snawerdt
    TI__Mastermind 42545 points
    Hi Andy,
    The short answer is that you can't. With three 16bit devices you're going to have four or five vias for each of the address command lines, one for escape from the K2G, one at each of the DDR memories and possibly one to get to the termination resistor. I'm going to check on this since this is a pretty common configuration. I will say the simulation on DDR3 interfaces is becoming close to necessary. This interface isn't running at the highest speeds but for other KeyStone II parts we always suggest it as a necessity.
    Regards,
    Bill