DRA62x (J5ECO): Differential impedance of DDR3

ytakano

Hello,

Differential impedance for DDR3 related is required 100ohm at minimum according to DRA62x (J5ECO) DM Table 9-28.
Customer asks that if the differential impedance has been achieved 80ohm,
is it acceptable or not?
What concerns can be thought?

Regards,
Yoshi Takano

over 8 years ago

0 Yordan Kamenov over 8 years ago

TI__Mastermind 42515 points

Hi,

I have forwarded your question to DDR expert.

Regards,
Yordan

0 Pavel Botev over 8 years ago

TI__Guru**** 170625 points

Hi Yoshi Takano,

I looked into DRA62x DM (SPRS778H), Table 9-28 CK and ADDR_CTRL Routing Specification, but I can not find there DDR3 differential impedance requirement.

Could you please specify on which table line exactly you see this?

Regards,
Pavel

0 ytakano over 8 years ago in reply to Pavel Botev

TI__Genius 9095 points

Hi Pavel,

In DRA62x DM (SPRS778H),

Table 9-28: Note 12)
   The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
   center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, Zo.

Table 9-29: Note 14)
   (same descriptions)

Regards,
Yoshi Takano

0 Yordan Kamenov over 8 years ago in reply to ytakano

TI__Mastermind 42515 points

Hi Yoshi,

just to inform you - Pavel is currently out of office so response may be delayed.

Regards,
Yordan

0 Pavel Botev over 8 years ago in reply to ytakano

TI__Guru**** 170625 points

Yoshi,

100ohm is the typical value. But we do not have minimum value, thus we can not guarantee that 80ohm will work properly, as this is very dependent of the custom board PCB design.

Regards,
Pavel

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DRA62x (J5ECO): Differential impedance of DDR3