In looking at the eMMC requirements for the AM5726/8, it looks like HS-200 mode is limited to 1.8V/1.2V I/O levels. The reference design has the eMMC and the MMC2 processor interfaces connected only to 3.3V. I believe this limits the eMMC to 50DDR mode which is 100Mbit max transfer rate. From JEDEC spec JESD84-B451 (eMMC version 4.51):
5.4.1 HS200 Bus Speed Mode
The HS200 mode offers the following features:
• SDR Data sampling method
• CLK frequency up to 200MHz Data rate – up to 200MB/s
• 4 or 8-bits bus width supported
• Single ended signaling with 4 selectable Drive Strength
• Signaling levels of 1.8V and 1.2V
• Tuning concept for Read Operations
So I am assuming that if I want to be able to run in HS200 mode on my design, I need to connect VCCQ(I/O pwr on eMMC) on the eMMC and VDDSVH11 (MMC2 pwr bus) on the processor to 1.8V, correct??
Also, do you know if there is a roadmap for HS400 support on the AM572x processors?
