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DSP 6455 EMIFA Speed Problem

burhan türkel
Intellectual 470 points

Other Parts Discussed in Thread: TMS320C6455

 

Dear Sir,
 
I am using the TMS320C6455 - 1GHz. DSK board. The problem is EMIF's speed. Here is my observations:
The read cycle is divided in 3 steps(setup,strobe and hold). These parameters are configurable in terms of ECLKOUT clock. I have measure the EMIFA clock source and found that it is 96MHz. I use a GEL file and I check the EMIF CE2 configuration register. If register set to 0x00240120,  a read of one array ( array equals to1byte)  takes 128ns. If register set to 0x00240000,  a read of one array  takes 36ns. These results make sense since I change the strobe width and make it 10 time smaller. 
I think 36ns is the minimum achievable time for one EMIFA read cycle. 
I need to use EMIF at maximum rate. How can achieve max rate? Please help me!
Burhan.

 

  • 0
    TI__Guru* 84110 points

    You definitely have a good grasp of most of the EMIF, in particular the Asynchronous mode of operation. You have experimented and taken measurements and obviously understand what you are talking about.

    burhan türkel said:
    The read cycle is divided in 3 steps(setup,strobe and hold).

    This is true for the Asynchronous mode of operation. Do you require that mode of operation, or can you use one of the Synchronous modes? They will have a much higher data rate. To what are you trying to connect the C6455's EMIF?

    burhan türkel said:
    I have measure the EMIFA clock source and found that it is bigger than 133 MHz.

    "bigger" is ambiguous here, to me. The datasheet says the AECLKIN period can be as low as 6ns, which is 166MHz. 166 is bigger than 133, but the period for 166MHz is smaller than the period for 133MHz. So it is not completely clear what you have measured.

    burhan türkel said:
    If register set to 0x00240120

    Forgive me, but I do not know the bit fields by memory, and the various fields affect the timing however you set them. If we need to discuss these register settings in detail, please help me out by using the bit field names so I do not have the chance to make reverse-assembly errors.

    burhan türkel said:
    I think 36ns is the minimum achievable time for one EMIFA read cycle.

    The minimum achievable time for an Asynchronous transfer is 3 AECLKOUT cycles. This is when SETUP = STROBE = HOLD = 0 as written to the bit fields, resulting in 1 cycle for each step in the actual read cycle. Since the minimum clock cycle is 6ns, you can beat 36ns by 50%.

    burhan türkel said:
    I need to use EMIF at maximum rate.

    What do you really require for your application? How much complexity can you stand? What are you trying to access via the EMIF? Do you plan to use all 64 bits?

  • 0 in reply to RandyP
    Intellectual 470 points

    RandyP said:
    This is true for the Asynchronous mode of operation. Do you require that mode of operation, or can you use one of the Synchronous modes? They will have a much higher data rate. To what are you trying to connect the C6455's EMIF?

    In fact I am going to measure data rate for Synchronous mode.

    We are going to interface ADC/DAC so we will connect FPGA between ADC and DSP. On the other posts, it is mentioned that FIFO will increase EDMA through-put since the overhead of EDMA stays the same for more data.

    RandyP said:
    "bigger" is ambiguous here, to me. The datasheet says the AECLKIN period can be as low as 6ns, which is 166MHz. 166 is bigger than 133, but the period for 166MHz is smaller than the period for 1333MHz. So it is not completely clear what you have measured.

    You are right it's ambiguous. I guess I was overloaded while posting. I correct it. The  AECLKIN is 96MHz.

    RandyP said:
    Forgive me, but I do not know the bit fields by memory, and the various fields affect the timing however you set them. If we need to discuss these register settings in detail, please help me out by using the bit field names so I do not have the chance to make reverse-assembly errors.

    CEn Configuration Registers bit field names are given in spru971e.pdf. The lsb is the zeroth bit.

    0x00240120 refers to 8-bit async, 10 cycle read/write strobe.

    RandyP said:
    The minimum achievable time for an Asynchronous transfer is 3 AECLKOUT cycles. This is when SETUP = STROBE = HOLD = 0 as written to the bit fields, resulting in 1 cycle for each step in the actual read cycle. Since the minimum clock cycle is 6ns, you can beat 36ns by 50%.

    Since AECLKOUT is 96MHz on DSKC6455 , 36ns is max. Thanks.

    RandyP said:
    What do you really require for your application? How much complexity can you stand? What are you trying to access via the EMIF? Do you plan to use all 64 bits?

    We are interfacing ADC and DAC via EMIF. The throughput must be 45 Msps. One sample equals to 32 bit data because 16bit ADCs are selected for converting I and Q data.

    Thanks for your answers. Any additional help will be greatful.

  • 0 in reply to burhan türkel
    TI__Guru* 84110 points

    Since the EMIF is 64 bits wide, your FPGA can spread out two sets of I and Q samples so that you can read two sets per setup/strobe/hold read cycle. I assume from your requirement for 45Msps of 32-bit samples, that you can lower that rate to 22.5Msps of 64-bit double samples.

    Since your data rate is very close to the max rate at which you can run Asynchronous Mode reads, my recommendation is for a simple FPGA design that uses the ARDY line to complete the read cycle. You might need to do a double-buffer on the FPGA, but there would be no need for a FIFO and its added complexity. The DMA channel that accesses the samples would just run continuously, and each read would wait for the ARDY signal.

    Good luck! Let us know how it works out.

  • 0 in reply to RandyP
    Intellectual 470 points
    Hi RandyP,
    Higher data rates are achieved by using EMIFA in sync. mode. 
    Thanks for your replies.
    PS. Is there well-known Signal Processing or Filtering  group/forum near here? :) Because I have questions about filtering.
  • 0 in reply to burhan türkel
    TI__Guru* 84110 points

    It sounds like you have things working well. That is great news.

    I recommend posting a new thread in this forum to ask your questions about filtering, and be sure to include the question about outside forums and user groups. I know there are some, but I have never participated there so I do not know where to point you. Since this thread is marked answered, it is less likely anyone will see your new question on this thread.