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TMS320C6678: Damping registers for Hyperlink pins

Naoki Kawada
Guru 19890 points
Part Number: TMS320C6678

Hi,

Datasheet defines the direction of following pins :

MCMRXFLCLK Output (Not input)
MCMRXFLDAT Output (Not input)
MCMTXFLCLK Input (Not output)
MCMTXFLDAT Input (Not output)

Is this really correct ? If yes, we believe the required damping register should be placed at the output side, but hardware design guide does not say so in Figure 22 HyperLink Bus DSP-to-DSP Connection.

Can you clarify ? I`m wandering if the datasheet descriptions is incorrect.

Best Regards,
Naoki Kawada

  • 0
    TI__Guru 65405 points
    Hi Naoki,

    I've forwarded this to the Hyperlink experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0
    TI__Guru**** 161600 points
    Hi,

    I think you mean damping RESISTORS not registers, right ?
    If so, as far as I know, they should be placed close to the output pins as shown in the hardware design guide, which means that the datasheed description is wrong. So your understanding should be correct.
    If my understanding is right the description in datasheet should be:
    MCMRXFLCLK -> Input
    MCMRXFLDAT -> Input
    MCMTXFLCLK -> Output
    MCMTXFLDAT -> Output

    If there may be doubt for the clock MCMRXFLCLK, I don't think that the receive data pin (MCMRXFLDAT) can be output buffer... Let me confirm this with the factory team.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 46460 points

    Yordan,

    The Data Manual is correct with its descriptions and buffer type.  The figure in the Hardware Design Guide is wrong as indicated by the initial post.  The FLCLK and FLDAT pins are names in reverse from the direction of the signals.  I do not know the history for the pin naming but this has always been true for HyperLink in both KeyStone-I and KeyStone-II

    Naoki,

    You are correct, the figure in the HDG provides incorrect information.  The Data Manual is correct and the EVM schematic is correct.  Also, series damping resistors are not needed on the data pins but only the clock pins.  Note that this drawing mistake is not significant since these nets must be short as this is a chip-to-chip interface.  Series damping resistors anywhere in the net will provide sufficient back-termination to prevent overshoot and ringing.

    Tom

  • 0 in reply to Tom Johnson 16214
    Guru 19890 points
    Hello Yordan and Tom,

    Thanks for your help. Ok, i'll suggest the same to the customer. I close the thread now.

    Best Regards,
    Naoki
  • 0 in reply to Tom Johnson 16214
    TI__Guru**** 161600 points
    Hi Tom,

    Thanks for the clarification about pin names.

    Best Regards,
    Yordan