• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 1006 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA2xx DDR hardware leveling timeout

rooney.hu
Intellectual 700 points


Hi all,

I'm now using a TDA2x EVB(Vayu) whose DDR is MT41K512M16HA-125, while my own production board uses W632GU6KB12K instead.

During EMIF_Config() in SBL, I got a hardware leveling timeout. I found that the bit 4 and bit 6  of SDRAM Status Register is 1. so it's Read DQS Gate Training Timeout and Write Leveling Timeout.

I found the a related link, but I cannot access the doc link in it.

(https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/307980?tisearch=e2e-sitesearch&keymatch=DDR%20read%20leveling%20timeout)

Does TI have some new guides for users to debug ? What can I do to deal with the Timeout exception?

My VisionSDK version is 2.9.1.0.  And I use BIOS only on all cores.

Thanks.