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Linux/AM4377: McSPI 64-bit transfer

Rohit Rampa
Intellectual 460 points
Part Number: AM4377

Tool/software: Linux

Hi

As part of our requirement, it is required to transfer 64 bit word in one SPI transaction.

Im able to keep the chip select low for the entire transaction, using the FORCE bit.

(I know I could keep the chip select low by making the the chip select line a GPIO and then control it according to the requirement)

However, Im able to transmit only 32 bit word.

Is this a limitation that I could only transfer a maximum of 32 bits in a single transaction.

From the TRM, I see that, we can transfer:

- 4 words in a single transaction if the word length is 8 bits

- 2 words if the word length is 16 bits

So could you please let me know if I would be able to do a 64 bit transfer in a single transaction(one chip select)

Thanks in advance

Rohit

  • 0
    TI__Guru**** 393215 points
    Hi,

    I think the TRM is quite clear on this. Access from CPU side is 32-bit wide, so there is no way to perform a 64-bit transfer in one access.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 460 points

    For 64 bit in one access, Im not able to do two 32 bit transfer(2 words), four 16 bit transfer(4words). But im able to do the 64 bit in one access if i can send eight 8 bit words(8 words of 8 bits length). This is beyond TRM. So, i need confirmation on this.

    Thanks.

  • 0 in reply to Rohit Rampa
    TI__Guru**** 393215 points
    What do you mean by "access"? Are you talking about accessing the external SPI device, or CPU access to the McSPI?
  • 0 in reply to Biser Gatchev-XID
    Intellectual 460 points

    Access = one single transaction/transmission cycle

    My concern is only about how many words/bits i should be able to do in one transmission cycle of the spi.

  • 0 in reply to Rohit Rampa
    Intellectual 460 points
    Hi Biser,

    Is there any update on my question?

    Thanks & Regards
  • 0 in reply to Rohit Rampa
    TI__Guru**** 161600 points
    Hi Rohit,

    The SPI interface in Sitara supports word length from 8 to 32 bits. So if you need to transfer a 64bit word you will have to keep the SPIEN active & transfer the data as two successive words.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 460 points

    Hi Yordan,

    Regrets for a delayed response.
    Yes, Im able to keeps the SPIEN active with the help of the FORCE bit between two successive words.
    Basically my requirement is to transfer 64 bit data.
    However, inspite of the keeping the SPIEN active, Im:
    1) Not able to transfer two 32 bit words (Slave just receives the first 32 bit words and the second 32 bit word is lost)
    2) Not able to transfer four 16 bit words (Slave just receives the first 2 sixteen bit words and the last 2 sixteen bit words are lost)

    But I can transfer 8 eight bit words(total 64 bit data) and the slave receives all of them.
    I know the SPI buffer is a 8 bit buffer. Does this 8 bit buffer has anything to do with this weird behavior(able to transfer 8 eight bit words but cannot successfully transmit the whole of two 32 bit words/ four 16 bit words))?

    Thanks
    Rohit

  • 0 in reply to Rohit Rampa
    TI__Guru**** 161600 points
    Hi,

    How did you configure your MCSPI_CHxCONF register, specifically the WL bit field?

    Also do you have anything else connected on your SPI? If not you can use 3-pin mode, where you don't need CS.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 460 points

    Hi Yordan,

    ( Intention is to transfer 64 bits. )

    MCSPI_CHxCONF:
    Transfer two 32 bit words
    Mode 0, WL - 32, FORCE bit set, Tx & Rx on a single line, SPIEN automated
    [ ** Keeping the chip select low while transfering two 32 bit words ** ]

    MCSPI_CHxCONF:
    Transfer four 16 bit words
    Mode 0, WL - 16, FORCE bit set, Tx & Rx on a single line, SPIEN automated
    [ ** Keeping the chip select low while transfering four 16 bit words ** ]

    MCSPI_CHxCONF:
    Transfer Eigh 8 bit words
    Mode 0, WL - 8, FORCE bit set, Tx & Rx on a single line, SPIEN automated
    [ ** Keeping the chip select low while transfering eight 8 bit words ** ]

    For my use case, chip select is very much required as the slave device is FPGA and it latches on while the chip select is low and on clock phase 0, polarity 0(Mode 0)

    Thanks & Regards
    Rohit