AM5728: OCM reset behavior

Roger Newbould31

Intellectual 310 points

Part Number: AM5728

Hi E2E Community

The Sitara AM5728 profides an OCM subsystem which consists of

OCMC_RAM1 with 512KiB of dedicated memory space
OCMC_RAM2 with 1024KiB of dedicated memory space
OCMC_RAM3 with 1024KiB of dedicated memory space

In figure 15-105 I can see that the OCMC_RAMx instances are reset with the CORE_RST signal coming from the PRCM block.

Is the content of the On-Chip Memory reset/cleared when the CPU is reset? Or just the corresponding controller?

Thanks.for your help.

Best regards,

Roger

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

The factory team have been notified. They will respond here.

0 Mukul Bhatnagar over 8 years ago

TI__Guru* 84615 points

Hi Roger

By CORE_RST , did you mean A15 reset or System reset?
If it is A15 or other cores initiated reset, this does not propagate to OCMC ram.
If it is system reset, the reset propagates to the controller. The behavior is OCMC RAM content is not cleared. But, this does not mean the OCMC RAM should be used to retain memory content across resets. We usually caution that contents can change across reset to a random value and therefore it should not be relied upon.

Hope this helps.

Regards
Mukul

0 Roger Newbould31 over 8 years ago in reply to Mukul Bhatnagar

Intellectual 310 points

By CORE_RST I mean a Sitara internal reset signal according to figure 15-105.

I guess that this is an internal reset domain. So how does this internal signal gets activated?

Thanks and best regards,

Roger

0 Mukul Bhatnagar over 8 years ago in reply to Roger Newbould31

TI__Guru* 84615 points

Hi Roger
You can refer to Table 3-34 pg 472 for the sources for CORE_RST internal signal.

Regards
Mukul

0 Roger Newbould31 over 8 years ago in reply to Mukul Bhatnagar

Intellectual 310 points

Hi Mukul

In a previous comment you mentioned that you don't recommend to use OCM for data which must remain unchanged throughout resets. It cannot be guarantied that the data doesn't get changed to some undefined value. Is that correct?

If so we cannot use the OCM and need to connect an external memory device.

Thanks and best regards,

Roger

0 Mukul Bhatnagar over 8 years ago in reply to Roger Newbould31

TI__Guru* 84615 points

Hi Roger
Sorry for the late response. Yes you should not use ocmc ram if you are expecting content to survive.
You will need to use an external flash like device, see the post here
e2e.ti.com/.../2165315

do note that by external memory if you meant DDR (say using self refresh), this is also not supported unfortunately for this family - for details you can look at erratas i727, i729.

Hope this helps.
Regards
Mukul

0 Roger Newbould31 over 8 years ago in reply to Mukul Bhatnagar

Intellectual 310 points

Hi Mukul

Thanks for the clarification and also the link to the other thread.

This has been helpful.

Best regards,

Roger

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AM5728: OCM reset behavior