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"Write Protect Should be Enabled for NAND Flash Boot" Advisory

skywalker
Prodigy 60 points

According to the Silicon Errata in http://focus.ti.com/lit/er/sprz251e/sprz251e.pdf

there is a problem with booting from NAND for Silcon revisions 1.1 and earlier.

Correct me if I am wrong, but this includes any device marked TMS320DM6467ZUT.

I am assuming from the advisory below that this issue has been resolved in Silicon Revision 3.0

(anything marked TMS320DM6467CZUT).

However, we can't seem to purchase any samples marked TMS320DM6467CZUT from the TI website.

All the samples are 1.1 or earlier. 

We would like to follow the advisory at least for the samples, but what is confusing

is that the DVEVM revision F schematics indicate the NAND WPn being pulled up

while the part on the DVEVM we have is Revision 1.1 or earlier. i.e TMS320DM6467ZUT,

i.e. the board is not following the recommended workaround in the advisory.

 

I was wondering if others have managed to boot from NAND on their DVEVMs (just to be clear, that means booting both UBL + Uboot from NAND).

Other posts in the forum seem to indicate problems booting from NAND on their DVEVMs.

------------------

Advisory 1.1.6 Write Protect Should be Enabled for NAND Flash Boot
Revision(s) Affected: 1.1 and earlier
Details: Write Protect should be enabled during NAND Boot; otherwise, the ARM RBL (ROM
Boot Loader) incorrectly detects the NAND ready status.
Workaround: Enable the NAND Flash Write Protect during boot. This requires the user to drive the
write protect pin on the NAND Flash. If the NAND Flash is used for more than a boot
device, then the user needs to design a workaround to control the write protect pin on
the NAND Flash using a GPIO pin.
This advisory will be fixed in a future major silicon revision.

  • 0
    TI__Mastermind 37340 points

    You are correct in your interpretation of the errata.  The EVM design contradicts the silicon errata, for the simple reason that the errata was not known at EVM design.  In internal tests, the EVM has not seen failures in NAND boot mode.  But other NAND devices that possibly run slower may cause an issue. To guarantee correct boot operation, the silicon errata should be followed.