Our customer sees that the default MPU_CLK Clock Setting by ROM Code is different from the description in the TRM (SPRUH73P). The TRM (SPRUH73P) describes "MPU ADPLLS is locked to provide 500 MHz for the A8", but MPU ADPLLS is set to 1 GHz with XIP boot for AM3352BZCZA100 on customer's board.
When using EVM which implements AM3358BZCZ00, MPU ADPLLS is locked to provide 1 GHz for the A8 with XIP boot or MMC0 boot. The details of the result are as follows:
For XIP boot:
PC -> 0x00020000
0x44E00420 CM_WKUP_CM_IDLEST_DPLL_MPU
0x44E00420 00000100
0x44E0042C CM_WKUP_CM_CLKSEL_DPLL_MPU
0x44E0042C 00000000
0x44E10040 Control_Module_control_status
0x44E10040 00480310
PC -> 0x08000000
0x44E00420 CM_WKUP_CM_IDLEST_DPLL_MPU
0x44E00420 00000001
0x44E0042C CM_WKUP_CM_CLKSEL_DPLL_MPU
0x44E0042C 0003E817
For MMC0 boot:
PC -> 0x00020000
0x44E00420 CM_WKUP_CM_IDLEST_DPLL_MPU
0x44E00420 00000100
0x44E0042C CM_WKUP_CM_CLKSEL_DPLL_MPU
0x44E0042C 00000000
0x44E10040 Control_Module_control_status
0x44E10040 00480317
PC -> 0x402F0400
0x44E00420 CM_WKUP_CM_IDLEST_DPLL_MPU
0x44E00420 00000001
0x44E0042C CM_WKUP_CM_CLKSEL_DPLL_MPU
0x44E0042C 0003E817
The supply voltage supplied to the VDD_MPU is 1.1 v during ROM boot. It does not meet the recommended operating conditions for Nitro (1GHz).
Is this not a problem?
Best regards,
Daisuke
