66AK2H14: How to modify DDR configuration in u-boot code?

Jin Tian

Part Number: 66AK2H14

Hi,I am using a customed board with 66AK2H14,Its design refers to the design of K2EVM-HK(TCI6638 evm).7271.66ak2h14_schematics.pdf

1 、EVM use a sodimm for DDR3A and 5 K4B4G1646D-BCK0（1600） chips for DDR3B.EVM use ECC.

My customed boaed modify the ddr3 design. I use 4 K4B4G1646D-BCK0 for DDR3A and 4 K4B4G1646D-BCK0 chips for DDR3B.I don't use ECC for DDR3A and DDR3B. page8/page9 of sch

My DDR3A and DDR3B design are same as EVM's DDR3B design except for NO ECC.

I find that EVM's DDR3A is dual RANK design ,but I use single Rank design .

2、EVM 's SGMII connect to PHY but my board 's SGMII connect to port0 of a eth switch(Boardcom BCM5389). port7 of BCM5389 connect to PHY. page11/page19/page18 of sch

Now I am doing u-boot in my board. I use ti-processor-sdk-linux-k2hk-evm-04.00.00.04.

I modify ti-processor-sdk-linux-k2hk-evm-04.00.00.04 / board-support /u-boot /board /ti /ks2_evm /ddr3_k2hk.c and ti-processor-sdk-linux-k2hk-evm-04.00.00.04 / board-support /u-boot /arch /arm /mach-keystone/ddr3.c line99 for DDR3A change

Fullscreen 6330.ddr3.c Download

/*
 * Keystone2: DDR3 initialization
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <asm/io.h>
#include <common.h>
#include <asm/arch/msmc.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/psc_defs.h>

#include <asm/ti-common/ti-edma3.h>

#define DDR3_EDMA_BLK_SIZE_SHIFT	10
#define DDR3_EDMA_BLK_SIZE		(1 << DDR3_EDMA_BLK_SIZE_SHIFT)
#define DDR3_EDMA_BCNT			0x8000
#define DDR3_EDMA_CCNT			1
#define DDR3_EDMA_XF_SIZE		(DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
#define DDR3_EDMA_SLOT_NUM		1

void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
	unsigned int tmp;

	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
		 & 0x00000001) != 0x00000001)
		;

	__raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);

	tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
	tmp &= ~(phy_cfg->pgcr1_mask);
	tmp |= phy_cfg->pgcr1_val;
	__raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);

	__raw_writel(phy_cfg->ptr0,   base + KS2_DDRPHY_PTR0_OFFSET);
	__raw_writel(phy_cfg->ptr1,   base + KS2_DDRPHY_PTR1_OFFSET);
	__raw_writel(phy_cfg->ptr3,  base + KS2_DDRPHY_PTR3_OFFSET);
	__raw_writel(phy_cfg->ptr4,  base + KS2_DDRPHY_PTR4_OFFSET);

	tmp =  __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
	tmp &= ~(phy_cfg->dcr_mask);
	tmp |= phy_cfg->dcr_val;
	__raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);

	__raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
	__raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
	__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
	__raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
	__raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
	__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
	__raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
	__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);

	__raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
	__raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
	__raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);

	__raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
		;

	if (cpu_is_k2g()) {
		clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET,
				phy_cfg->datx8_2_mask,
				phy_cfg->datx8_2_val);

		clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET,
				phy_cfg->datx8_3_mask,
				phy_cfg->datx8_3_val);

		clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET,
				phy_cfg->datx8_4_mask,
				phy_cfg->datx8_4_val);

		clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET,
				phy_cfg->datx8_5_mask,
				phy_cfg->datx8_5_val);

		clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET,
				phy_cfg->datx8_6_mask,
				phy_cfg->datx8_6_val);

		clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET,
				phy_cfg->datx8_7_mask,
				phy_cfg->datx8_7_val);

		clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET,
				phy_cfg->datx8_8_mask,
				phy_cfg->datx8_8_val);
	}

	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1);
	//Modified for close ecc
	__raw_writel(0x7C000E80, base + KS2_DDRPHY_DATX8_8_OFFSET);
	__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
		;
}

void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
{
	__raw_writel(emif_cfg->sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);
	__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
	__raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
	__raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
	__raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
	__raw_writel(emif_cfg->zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);
	__raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
}

int ddr3_ecc_support_rmw(u32 base)
{
	u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);

	/* Check the DDR3 controller ID reg if the controllers
	   supports ECC RMW or not */
	if (value == 0x40461C02)
		return 1;

	return 0;
}

static void ddr3_ecc_config(u32 base, u32 value)
{
	u32 data;

	__raw_writel(value,  base + KS2_DDR3_ECC_CTRL_OFFSET);
	udelay(100000); /* delay required to synchronize across clock domains */

	if (value & KS2_DDR3_ECC_EN) {
		/* Clear the 1-bit error count */
		data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
		__raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);

		/* enable the ECC interrupt */
		__raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
			     KS2_DDR3_WR_ECC_ERR_SYS,
			     base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);

		/* Clear the ECC error interrupt status */
		__raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
			     KS2_DDR3_WR_ECC_ERR_SYS,
			     base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
	}
}

static void ddr3_reset_data(u32 base, u32 ddr3_size)
{
	u32 mpax[2];
	u32 seg_num;
	u32 seg, blks, dst, edma_blks;
	struct edma3_slot_config slot;
	struct edma3_channel_config edma_channel;
	u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };

	/* Setup an edma to copy the 1k block to the entire DDR */
	puts("\nClear entire DDR3 memory to enable ECC\n");

	/* save the SES MPAX regs */
	if (cpu_is_k2g())
		msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
	else
		msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);

	/* setup edma slot 1 configuration */
	slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
		   EDMA3_SLOPT_COMP_CODE(0) |
		   EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
	slot.bcnt = DDR3_EDMA_BCNT;
	slot.acnt = DDR3_EDMA_BLK_SIZE;
	slot.ccnt = DDR3_EDMA_CCNT;
	slot.src_bidx = 0;
	slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
	slot.src_cidx = 0;
	slot.dst_cidx = 0;
	slot.link = EDMA3_PARSET_NULL_LINK;
	slot.bcntrld = 0;
	edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);

	/* configure quik edma channel */
	edma_channel.slot = DDR3_EDMA_SLOT_NUM;
	edma_channel.chnum = 0;
	edma_channel.complete_code = 0;
	/* event trigger after dst update */
	edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
	qedma3_start(KS2_EDMA0_BASE, &edma_channel);

	/* DDR3 size in segments (4KB seg size) */
	seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);

	for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
		/* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
		   access slave interface so that edma driver can access */
		if (cpu_is_k2g()) {
			msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
					     base >> KS2_MSMC_SEG_SIZE_SHIFT,
					     KS2_MSMC_DST_SEG_BASE + seg,
					     MPAX_SEG_2G);
		} else {
			msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0,
					     base >> KS2_MSMC_SEG_SIZE_SHIFT,
					     KS2_MSMC_DST_SEG_BASE + seg,
					     MPAX_SEG_2G);
		}

		if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
			edma_blks = KS2_MSMC_MAP_SEG_NUM <<
					(KS2_MSMC_SEG_SIZE_SHIFT
					- DDR3_EDMA_BLK_SIZE_SHIFT);
		else
			edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
					- DDR3_EDMA_BLK_SIZE_SHIFT);

		/* Use edma driver to scrub 2GB DDR memory */
		for (dst = base, blks = 0; blks < edma_blks;
		     blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
			edma3_set_src_addr(KS2_EDMA0_BASE,
					   edma_channel.slot, (u32)edma_src);
			edma3_set_dest_addr(KS2_EDMA0_BASE,
					    edma_channel.slot, (u32)dst);

			while (edma3_check_for_transfer(KS2_EDMA0_BASE,
							&edma_channel))
				udelay(10);
		}
	}

	qedma3_stop(KS2_EDMA0_BASE, &edma_channel);

	/* restore the SES MPAX regs */
	if (cpu_is_k2g())
		msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
	else
		msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
}

static void ddr3_ecc_init_range(u32 base)
{
	u32 ecc_val = KS2_DDR3_ECC_EN;
	u32 rmw = ddr3_ecc_support_rmw(base);

	if (rmw)
		ecc_val |= KS2_DDR3_ECC_RMW_EN;

	__raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);

	ddr3_ecc_config(base, ecc_val);
}

void ddr3_enable_ecc(u32 base, int test)
{
	u32 ecc_val = KS2_DDR3_ECC_ENABLE;
	u32 rmw = ddr3_ecc_support_rmw(base);

	if (test)
		ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;

	if (!rmw) {
		if (!test)
			/* by default, disable ecc when rmw = 0 and no
			   ecc test */
			ecc_val = 0;
	} else {
		ecc_val |= KS2_DDR3_ECC_RMW_EN;
	}

	ddr3_ecc_config(base, ecc_val);
}

void ddr3_disable_ecc(u32 base)
{
	ddr3_ecc_config(base, 0);
}

#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
static void cic_init(u32 base)
{
	/* Disable CIC global interrupts */
	__raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);

	/* Set to normal mode, no nesting, no priority hold */
	__raw_writel(0, base + KS2_CIC_CTRL);
	__raw_writel(0, base + KS2_CIC_HOST_CTRL);

	/* Enable CIC global interrupts */
	__raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
}

static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
{
	/* Map the system interrupt to a CIC channel */
	__raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);

	/* Enable CIC system interrupt */
	__raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);

	/* Enable CIC Host interrupt */
	__raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
}

static void ddr3_map_ecc_cic2_irq(u32 base)
{
	cic_init(base);
	cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
			   KS2_CIC2_DDR3_ECC_IRQ_NUM);
}
#endif

void ddr3_init_ecc(u32 base, u32 ddr3_size)
{
	if (!ddr3_ecc_support_rmw(base)) {
		ddr3_disable_ecc(base);
		return;
	}

	ddr3_ecc_init_range(base);
	ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);

	/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
	ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
#endif
	ddr3_enable_ecc(base, 0);
}

void ddr3_check_ecc_int(u32 base)
{
	char *env;
	int ecc_test = 0;
	u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);

	env = getenv("ecc_test");
	if (env)
		ecc_test = simple_strtol(env, NULL, 0);

	if (value & KS2_DDR3_WR_ECC_ERR_SYS)
		puts("DDR3 ECC write error interrupted\n");

	if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
		puts("DDR3 ECC 2-bit error interrupted\n");

		if (!ecc_test) {
			puts("Reseting the device ...\n");
			reset_cpu(0);
		}
	}

	value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
	if (value) {
		printf("1-bit ECC err count: 0x%x\n", value);
		value = __raw_readl(base +
				    KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
		printf("1-bit ECC err address log: 0x%x\n", value);
	}
}

void ddr3_reset_ddrphy(void)
{
	u32 tmp;

	/* Assert DDR3A  PHY reset */
	tmp = readl(KS2_DDR3APLLCTL1);
	tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
	writel(tmp, KS2_DDR3APLLCTL1);

	/* wait 10us to catch the reset */
	udelay(10);

	/* Release DDR3A PHY reset */
	tmp = readl(KS2_DDR3APLLCTL1);
	tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
	__raw_writel(tmp, KS2_DDR3APLLCTL1);
}

#ifdef CONFIG_SOC_K2HK
/**
 * ddr3_reset_workaround - reset workaround in case if leveling error
 * detected for PG 1.0 and 1.1 k2hk SoCs
 */
void ddr3_err_reset_workaround(void)
{
	unsigned int tmp;
	unsigned int tmp_a;
	unsigned int tmp_b;

	/*
	 * Check for PGSR0 error bits of DDR3 PHY.
	 * Check for WLERR, QSGERR, WLAERR,
	 * RDERR, WDERR, REERR, WEERR error to see if they are set or not
	 */
	tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
	tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);

	if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
		printf("DDR Leveling Error Detected!\n");
		printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
		printf("DDR3B PGSR0 = 0x%x\n", tmp_b);

		/*
		 * Write Keys to KICK registers to enable writes to registers
		 * in boot config space
		 */
		__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
		__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);

		/*
		 * Move DDR3A Module out of reset isolation by setting
		 * MDCTL23[12] = 0
		 */
		tmp_a = __raw_readl(KS2_PSC_BASE +
				    PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));

		tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
		__raw_writel(tmp_a, KS2_PSC_BASE +
			     PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));

		/*
		 * Move DDR3B Module out of reset isolation by setting
		 * MDCTL24[12] = 0
		 */
		tmp_b = __raw_readl(KS2_PSC_BASE +
				    PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
		tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
		__raw_writel(tmp_b, KS2_PSC_BASE +
			     PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));

		/*
		 * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
		 * to RSTCTRL and RSTCFG
		 */
		tmp = __raw_readl(KS2_RSTCTRL);
		tmp &= KS2_RSTCTRL_MASK;
		tmp |= KS2_RSTCTRL_KEY;
		__raw_writel(tmp, KS2_RSTCTRL);

		/*
		 * Set PLL Controller to drive hard reset on SW trigger by
		 * setting RSTCFG[13] = 0
		 */
		tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
		tmp &= ~KS2_RSTYPE_PLL_SOFT;
		__raw_writel(tmp, KS2_RSTCTRL_RSCFG);

		reset_cpu(0);
	}
}
#endif

Fullscreen 0044.ddr3_k2hk.c Download

/*
 * Keystone2: DDR3 initialization
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>

struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
struct ddr3_phy_config ddr3phy_1600_2g = {
	.pllcr          = 0x0001C000ul,
	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
	.ptr0           = 0x42C21590ul,
	.ptr1           = 0xD05612C0ul,
	.ptr2           = 0, /* not set in gel */
	.ptr3           = 0x0D861A80ul,
	.ptr4           = 0x0C827100ul,
	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
	.dcr_val        = ((1 << 10)),
	.dtpr0          = 0x9D9CBB66ul,
	.dtpr1          = 0x32868400ul,
	.dtpr2          = 0x5002D200ul,
	.mr0            = 0x00001C70ul,
	.mr1            = 0x00000006ul,
	.mr2            = 0x00000018ul,
	.dtcr           = 0x710035C7ul,
	.pgcr2          = 0x00F07A12ul,
	.zq0cr1         = 0x0001005Dul,
	.zq1cr1         = 0x0001005Bul,
	.zq2cr1         = 0x0001005Bul,
	.pir_v1         = 0x00000033ul,
	.datx8_2_mask	= 0x00000001ul,
	.datx8_2_val	= 0x7C000E81ul,
	.datx8_3_mask	= 0x00000001ul,
	.datx8_3_val	= 0x7C000E81ul,
	.datx8_4_mask	= 0x00000001ul,
	.datx8_4_val	= 0x7C000E81ul,
	.datx8_5_mask	= 0x00000001ul,
	.datx8_5_val	= 0x7C000E81ul,
	.datx8_6_mask	= 0x00000001ul,
	.datx8_6_val	= 0x7C000E81ul,
	.datx8_7_mask	= 0x00000001ul,
	.datx8_7_val	= 0x7C000E81ul,
	.datx8_8_mask	= 0x00000001ul,
	.datx8_8_val	= 0x7C000E80ul,
	.pir_v2         = 0x0000FF81ul,
};

struct ddr3_emif_config ddr3_1600_2g = {
	.sdcfg          = 0x6200CE62ul,
	.sdtim1         = 0x166C9875ul,
	.sdtim2         = 0x00001D4Aul,
	.sdtim3         = 0x435DFF53ul,
	.sdtim4         = 0x543F0CFFul,
	.zqcfg          = 0x70073200ul,
	.sdrfc          = 0x00001869ul,
};
u32 ddr3_init(void)
{
	u32 ddr3_size;
	struct ddr3_spd_cb spd_cb;
	u32 value = 0;
	char DDR3_name[] = {"4 K4BG1646D-1600"};
/*	if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
		printf("Sorry, I don't know how to configure DDR3A.\n"
		       "Bye :(\n");
		for (;;)
			;
	}*/
	value = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
	printf("DDR3 status: 0x%x\n", value);
	memcpy(&spd_cb.dimm_name,DDR3_name,30);
	memcpy(&spd_cb.emif_cfg,&ddr3_1600_2g,sizeof(struct ddr3_emif_config));
	memcpy(&spd_cb.phy_cfg,&ddr3phy_1600_2g,sizeof(struct ddr3_phy_config));
	spd_cb.ddrspdclock = 1600;
	spd_cb.ddr_size_gbyte = 2;

	printf("Detected  [%s]\n",spd_cb.dimm_name);
	if ((cpu_revision() > 1) ||
	    (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) {
		printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
		if (spd_cb.ddrspdclock == 1600)
			init_pll(&ddr3a_400);
		else
			init_pll(&ddr3a_333);
	}

	if (cpu_revision() > 0) {
		if (cpu_revision() > 1) {
			/* PG 2.0 */
			/* Reset DDR3A PHY after PLL enabled */
			ddr3_reset_ddrphy();
			spd_cb.phy_cfg.zq0cr1 |= 0x10000;
			spd_cb.phy_cfg.zq1cr1 |= 0x10000;
			spd_cb.phy_cfg.zq2cr1 |= 0x10000;
		}
		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);

		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);

		ddr3_size = spd_cb.ddr_size_gbyte;
	} else {
		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
		spd_cb.emif_cfg.sdcfg |= 0x1000;
		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
		ddr3_size = spd_cb.ddr_size_gbyte / 2;
	}
	printf("DRAM: %d GiB (includes reported below)\n", ddr3_size);

	/* Apply the workaround for PG 1.0 and 1.1 Silicons */
	if (cpu_revision() <= 1)
		ddr3_err_reset_workaround();

	//tj
	value = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
	printf("DDR3 status: 0x%x\n", value);
	printf("ddr3_init parameter input done\n");
	return ddr3_size;
}

I modify ti-processor-sdk-linux-k2hk-evm-04.00.00.04 / board-support /u-boot /arch /arm /dts / keystone-k2hk-netcp.dtsi line 169and line174 for eth change. Idtsi file can upload,I change .dtsi to .c

Fullscreen keystone-k2hk-netcp.c Download

/*
 * Device Tree Source for Keystone 2 Hawking Netcp driver
 *
 * Copyright 2015 Texas Instruments, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

qmss: qmss@2a40000 {
	compatible = "ti,keystone-navigator-qmss";
	dma-coherent;
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&chipclk13>;
	ranges;
	queue-range	= <0 0x4000>;
	linkram0	= <0x100000 0x8000>;
	linkram1	= <0x0 0x10000>;

	qmgrs {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		qmgr0 {
			managed-queues = <0 0x2000>;
			reg = <0x2a40000 0x20000>,
			      <0x2a06000 0x400>,
			      <0x2a02000 0x1000>,
			      <0x2a03000 0x1000>,
			      <0x23a80000 0x20000>,
			      <0x2a80000 0x20000>;
			reg-names = "peek", "status", "config",
				    "region", "push", "pop";
		};

		qmgr1 {
			managed-queues = <0x2000 0x2000>;
			reg = <0x2a60000 0x20000>,
			      <0x2a06400 0x400>,
			      <0x2a04000 0x1000>,
			      <0x2a05000 0x1000>,
			      <0x23aa0000 0x20000>,
			      <0x2aa0000 0x20000>;
			reg-names = "peek", "status", "config",
				    "region", "push", "pop";
		};
	};
	queue-pools {
		qpend {
			qpend-0 {
				qrange = <658 8>;
				interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
					     0 43 0xf04 0 44 0xf04 0 45 0xf04
					     0 46 0xf04 0 47 0xf04>;
			};
			qpend-1 {
				qrange = <8704 16>;
				interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
					      0 51 0xf04 0 52 0xf04 0 53 0xf04
					      0 54 0xf04 0 55 0xf04 0 56 0xf04
					      0 57 0xf04 0 58 0xf04 0 59 0xf04
					      0 60 0xf04 0 61 0xf04 0 62 0xf04
					      0 63 0xf04>;
				qalloc-by-id;
			};
			qpend-2 {
				qrange = <8720 16>;
				interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
					      0 59 0xf04 0 68 0xf04 0 69 0xf04
					      0 70 0xf04 0 71 0xf04 0 72 0xf04
					      0 73 0xf04 0 74 0xf04 0 75 0xf04
					      0 76 0xf04 0 77 0xf04 0 78 0xf04
					      0 79 0xf04>;
			};
		};
		general-purpose {
			gp-0 {
				qrange = <4000 64>;
			};
			netcp-tx {
				qrange = <640 9>;
				qalloc-by-id;
			};
			netcpx-tx {
				qrange = <8752 8>;
				qalloc-by-id;
			};
		};
	};
	descriptor-regions {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		region-12 {
			id = <12>;
			region-spec = <8192 128>;	/* num_desc desc_size */
			link-index = <0x4000>;
		};
	};
}; /* qmss */

knav_dmas: knav_dmas@0 {
	compatible = "ti,keystone-navigator-dma";
	clocks = <&papllclk>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	ti,navigator-cloud-address = <0x23a80000 0x23a90000
				   0x23aa0000 0x23ab0000>;

	dma_gbe: dma_gbe@0 {
		reg = <0x2004000 0x100>,
			  <0x2004400 0x120>,
			  <0x2004800 0x300>,
			  <0x2004c00 0x120>,
			  <0x2005000 0x400>;
		reg-names = "global", "txchan", "rxchan",
				"txsched", "rxflow";
	};

	dma_srio: dma_srio@0 {
		reg = <0x2901000 0x020>,
			<0x2901400 0x200>,
			<0x2901800 0x200>,
			<0x2901c00 0x200>,
			<0x2902000 0x280>;
		reg-names = "global", "txchan", "rxchan",
				"txsched", "rxflow";
	};
};

netcp: netcp@2000000 {
	reg = <0x2620110 0x8>;
	reg-names = "efuse";
	compatible = "ti,netcp-1.0";
	#address-cells = <1>;
	#size-cells = <1>;

	/* NetCP address range */
	ranges  = <0 0x2000000 0x100000>;

	clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
	dma-coherent;

	ti,navigator-dmas = <&dma_gbe 22>,
			<&dma_gbe 23>,
			<&dma_gbe 8>;
	ti,navigator-dma-names = "netrx0", "netrx1", "nettx";

	netcp-devices {
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;
		gbe@90000 { /* ETHSS */
			#address-cells = <1>;
			#size-cells = <1>;
			label = "netcp-gbe";
			compatible = "ti,netcp-gbe";
			reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>;
			/* enable-ale; */
			tx-queue = <648>;
			tx-channel = "nettx";

			interfaces {
				gbe0: interface-0 {
					slave-port = <0>;
					link-interface = <0>;
					phy-handle = <&ethphy0>;
				};
				gbe1: interface-1 {
					slave-port = <1>;
					link-interface = <0>;
					phy-handle = <&ethphy1>;
				};
			};

			secondary-slave-ports {
				port-2 {
					slave-port = <2>;
					link-interface	= <2>;
				};
				port-3 {
					slave-port = <3>;
					link-interface	= <2>;
				};
			};
		};
	};

	netcp-interfaces {
		interface-0 {
			rx-channel = "netrx0";
			rx-pool = <1024 12>;
			tx-pool = <1024 12>;
			rx-queue-depth = <128 128 0 0>;
			rx-buffer-size = <1518 4096 0 0>;
			rx-queue = <8704>;
			tx-completion-queue = <8706>;
			efuse-mac = <1>;
			netcp-gbe = <&gbe0>;

		};
		interface-1 {
			rx-channel = "netrx1";
			rx-pool = <1024 12>;
			tx-pool = <1024 12>;
			rx-queue-depth = <128 128 0 0>;
			rx-buffer-size = <1518 4096 0 0>;
			rx-queue = <8705>;
			tx-completion-queue = <8707>;
			efuse-mac = <0>;
			local-mac-address = [02 18 31 7e 3e 6f];
			netcp-gbe = <&gbe1>;
		};
	};
};

Besides,I add #define DEBUG 1 in ti-processor-sdk-linux-k2hk-evm-04.00.00.04 / board-support /u-boot /include /common.h line98,so I can see debug information in u-boot console.

When I do U-boot ,the u-boot console print:

[17:34:13.277] initcall: 0c042ed1
[17:34:13.277] 
[17:34:13.294] U-Boot 2017.01-00319-gf3ebc3d-dirty (Aug 16 2017 - 15:44:43 +0800)
[17:34:13.294] 
[17:34:13.294] initcall: 0c00dde5
[17:34:13.294] U-Boot code: 0C000000 -> 0C06A880  BSS: -> 0C0CBE98
[17:34:13.294] initcall: 0c00104d
[17:34:13.294] CPU: 66AK2Hx SR2.0
[17:34:13.310] initcall: 0c00260d
[17:34:13.310] initcall: 0c00e225
[17:34:13.310] Model: Texas Instruments Keystone 2 Kepler/Hawking EVM
[17:34:13.310] initcall: 0c00de15
[17:34:13.310] I2C:   ready
[17:34:13.310] initcall: 0c00de05
[17:34:13.310] DRAM:  initcall: 0c002315
[17:34:13.327] DDR3 status: 0xb000001a
[17:34:13.327] Detected  [4 K4BG1646D-1600]
[17:34:13.327] DDR3 speed 1600
[17:34:13.327] DRAM: 2 GiB (includes reported below)
[17:34:13.341] DDR3 status: 0xb0000fff
[17:34:13.341] ddr3_init parameter input done
[17:34:13.341] 
[17:34:13.437] Clear entire DDR3 memory to enable ECC
[17:34:13.437] initcall: 0c00dff9
[17:34:13.743] Monitor len: 000CBE98
[17:34:13.743] Ram size: 40000000
[17:34:13.743] Ram top: C0000000
[17:34:13.743] initcall: 0c00dc91
[17:34:13.757] initcall: 0c00dd9d
[17:34:13.757] TLB table from bfff0000 to bfff4000
[17:34:13.757] initcall: 0c00df29
[17:34:13.757] initcall: 0c00dd5d
[17:34:13.757] Reserving 815k for U-Boot at: bff24000
[17:34:13.757] initcall: 0c00dd39
[17:34:13.757] Reserving 33024k for malloc() at: bdee4000
[17:34:13.773] initcall: 0c00dee9
[17:34:13.773] Reserving 88 Bytes for Board Info at: bdee3fa8
[17:34:13.773] initcall: 0c00df2d
[17:34:13.773] initcall: 0c00dd11
[17:34:13.773] Reserving 200 Bytes for Global Data at: bdee3ee0
[17:34:13.789] initcall: 0c00dcc1
[17:34:13.789] Reserving 33728 Bytes for FDT at: bdedbb20
[17:34:13.789] initcall: 0c00df21
[17:34:13.789] initcall: 0c00e061
[17:34:13.789] initcall: 0c00dfdd
[17:34:13.789] initcall: 0c00df39
[17:34:13.789] 
[17:34:13.789] RAM Configuration:
[17:34:13.789] Bank #0: 80000000 1 GiB
[17:34:13.805] Bank #1: 0 0 Bytes
[17:34:13.805] 
[17:34:13.805] DRAM:  1 GiB
[17:34:13.805] initcall: 0c00dcad
[17:34:13.805] New Stack Pointer is: bdedbb00
[17:34:13.805] initcall: 0c00debd
[17:34:13.805] initcall: 0c00de65
[17:34:13.805] Relocation Offset is: b3f24000
[17:34:13.805] Relocating to bff24000, new gd at bdee3ee0, sp at bdedbb00
[17:34:13.821] initcall: bff321ff
[17:34:13.821] initcall: bff320a1
[17:34:13.821] initcall: 0c00e1f1 (relocated to bff321f1)
[17:34:13.837] initcall: 0c00e1c9 (relocated to bff321c9)
[17:34:13.837] efi_runtime_relocate: Relocating to offset=bff24000
[17:34:13.837] efi_runtime_relocate: Setting bff8e730 to bff8e788
[17:34:13.853] efi_runtime_relocate: Setting bff8e73c to bff6cc40
[17:34:13.853] efi_runtime_relocate: Setting bff8e744 to bff6cc4c
[17:34:13.853] efi_runtime_relocate: Setting bff8e74c to bff6cc4c
[17:34:13.853] efi_runtime_relocate: Setting bff8e750 to bff8e7a0
[17:34:13.869] efi_runtime_relocate: Setting bff8e754 to bff6c1b0
[17:34:13.869] efi_runtime_relocate: Setting bff8e75c to bff8e760
[17:34:13.869] efi_runtime_relocate: Setting bff8e7b8 to bff60e25
[17:34:13.869] efi_runtime_relocate: Setting bff8e7bc to bff8e705
[17:34:13.885] efi_runtime_relocate: Setting bff8e7c0 to bff8e6fd
[17:34:13.885] efi_runtime_relocate: Setting bff8e7c4 to bff8e6fd
[17:34:13.885] efi_runtime_relocate: Setting bff8e7c8 to bff60f61
[17:34:13.901] efi_runtime_relocate: Setting bff8e7cc to bff8e70d
[17:34:13.901] efi_runtime_relocate: Setting bff8e7d0 to bff8e705
[17:34:13.901] efi_runtime_relocate: Setting bff8e7d4 to bff8e705
[17:34:13.901] efi_runtime_relocate: Setting bff8e7d8 to bff8e705
[17:34:13.917] efi_runtime_relocate: Setting bff8e7dc to bff8e705
[17:34:13.917] efi_runtime_relocate: Setting bff8e7e0 to bff60e2d
[17:34:13.917] initcall: 0c00e1fb (relocated to bff321fb)
[17:34:13.933] initcall: 0c00e19d (relocated to bff3219d)
[17:34:13.933] Pre-reloc malloc() used 0x10c bytes (0 KB)
[17:34:13.933] using memory 0xbdee4000-0xbff24000 for malloc()
[17:34:13.933] initcall: 0c00e0b5 (relocated to bff320b5)
[17:34:13.981] initcall: 0c00e09d (relocated to bff3209d)
[17:34:13.997] initcall: 0c00e18b (relocated to bff3218b)
[17:34:13.997] uclass_find_device_by_seq: 0 -1
[17:34:13.997] uclass_find_device_by_seq: 0 0
[17:34:13.997]    - -1 -1
[17:34:13.997]    - not found
[17:34:13.997] bind node chosen
[17:34:13.997] Device 'chosen' has no compatible string
[17:34:14.013] bind node aliases
[17:34:14.013] Device 'aliases' has no compatible string
[17:34:14.013] bind node memory
[17:34:14.013] Device 'memory' has no compatible string
[17:34:14.013] bind node interrupt-controller
[17:34:14.013]    - attempt to match compatible string 'arm,cortex-a15-gic'
[17:34:14.029] No match for node 'interrupt-controller'
[17:34:14.029] bind node timer
[17:34:14.029]    - attempt to match compatible string 'arm,armv7-timer'
[17:34:14.029] No match for node 'timer'
[17:34:14.045] bind node pmu
[17:34:14.045]    - attempt to match compatible string 'arm,cortex-a15-pmu'
[17:34:14.045] No match for node 'pmu'
[17:34:14.045] bind node soc
[17:34:14.045]    - attempt to match compatible string 'ti,keystone'
[17:34:14.061]    - attempt to match compatible string 'simple-bus'
[17:34:14.061]    - found match at 'generic_simple_bus'
[17:34:14.061] fdtdec_get_int_array: ranges
[17:34:14.061] get_prop_check_min_len: ranges
[17:34:14.061] bind node pll-controller@02310000
[17:34:14.077]    - attempt to match compatible string 'ti,keystone-pllctrl'
[17:34:14.077]    - attempt to match compatible string 'syscon'
[17:34:14.077] No match for node 'pll-controller@02310000'
[17:34:14.077] bind node device-state-control@02620000
[17:34:14.093]    - attempt to match compatible string 'ti,keystone-devctrl'
[17:34:14.093]    - attempt to match compatible string 'syscon'
[17:34:14.093] No match for node 'device-state-control@02620000'
[17:34:14.109] bind node reset-controller
[17:34:14.109]    - attempt to match compatible string 'ti,keystone-reset'
[17:34:14.109] No match for node 'reset-controller'
[17:34:14.109] bind node clocks
[17:34:14.109] Device 'clocks' has no compatible string
[17:34:14.125] bind node serial@02530c00
[17:34:14.125]    - attempt to match compatible string 'ns16550a'
[17:34:14.125]    - found match at 'ns16550_serial'
[17:34:14.125] Looking for 'serial' at 17116, name serial@02530c00
[17:34:14.141]    - serial0, /soc/serial@02530c00
[17:34:14.141] Found seq 0
[17:34:14.141] Bound device serial@02530c00 to soc
[17:34:14.141] bind node serial@02531000
[17:34:14.141]    - attempt to match compatible string 'ns16550a'
[17:34:14.157]    - found match at 'ns16550_serial'
[17:34:14.157] Looking for 'serial' at 17272, name serial@02531000
[17:34:14.157]    - serial0, /soc/serial@02530c00
[17:34:14.157]    - spi0, /soc/spi@21000400
[17:34:14.157]    - spi1, /soc/spi@21000600
[17:34:14.173]    - spi2, /soc/spi@21000800
[17:34:14.173] Not found
[17:34:14.173] Bound device serial@02531000 to soc
[17:34:14.173] bind node i2c@2530000
[17:34:14.173]    - attempt to match compatible string 'ti,davinci-i2c'
[17:34:14.189] No match for node 'i2c@2530000'
[17:34:14.189] bind node i2c@2530400
[17:34:14.189]    - attempt to match compatible string 'ti,davinci-i2c'
[17:34:14.189] No match for node 'i2c@2530400'
[17:34:14.189] bind node i2c@2530800
[17:34:14.189]    - attempt to match compatible string 'ti,davinci-i2c'
[17:34:14.205] No match for node 'i2c@2530800'
[17:34:14.205] bind node spi@21000400
[17:34:14.205]    - attempt to match compatible string 'ti,dm6441-spi'
[17:34:14.205]    - found match at 'davinci_spi'
[17:34:14.221] Looking for 'spi' at 17952, name spi@21000400
[17:34:14.221]    - serial0, /soc/serial@02530c00
[17:34:14.221]    - spi0, /soc/spi@21000400
[17:34:14.221] Found seq 0
[17:34:14.221] bind node n25q128a11@0
[17:34:14.221]    - attempt to match compatible string 'Micron,n25q128a11'
[17:34:14.237]    - attempt to match compatible string 'spi-flash'
[17:34:14.237]    - found match at 'spi_flash_std'
[17:34:14.237] fdtdec_get_int: reg: 0x0 (0)
[17:34:14.237] fdtdec_get_int: spi-max-frequency: 0x337f980 (54000000)
[17:34:14.253] fdtdec_get_bool: spi-cpol
[17:34:14.253] fdtdec_get_bool: spi-cpha
[17:34:14.253] fdtdec_get_bool: spi-cs-high
[17:34:14.253] fdtdec_get_bool: spi-3wire
[17:34:14.253] fdtdec_get_bool: spi-half-duplex
[17:34:14.253] fdtdec_get_uint: spi-tx-bus-width: (not found)
[17:34:14.269] fdtdec_get_uint: spi-rx-bus-width: (not found)
[17:34:14.269] Bound device n25q128a11@0 to spi@21000400
[17:34:14.269] Bound device spi@21000400 to soc
[17:34:14.269] bind node spi@21000600
[17:34:14.286]    - attempt to match compatible string 'ti,dm6441-spi'
[17:34:14.286]    - found match at 'davinci_spi'
[17:34:14.286] Looking for 'spi' at 18424, name spi@21000600
[17:34:14.286]    - serial0, /soc/serial@02530c00
[17:34:14.301]    - spi0, /soc/spi@21000400
[17:34:14.301]    - spi1, /soc/spi@21000600
[17:34:14.301] Found seq 1
[17:34:14.301] Bound device spi@21000600 to soc
[17:34:14.301] bind node spi@21000800
[17:34:14.301]    - attempt to match compatible string 'ti,dm6441-spi'
[17:34:14.317]    - found match at 'davinci_spi'
[17:34:14.317] Looking for 'spi' at 18600, name spi@21000800
[17:34:14.317]    - serial0, /soc/serial@02530c00
[17:34:14.317]    - spi0, /soc/spi@21000400
[17:34:14.317]    - spi1, /soc/spi@21000600
[17:34:14.338]    - spi2, /soc/spi@21000800
[17:34:14.338] Found seq 2
[17:34:14.338] Bound device spi@21000800 to soc
[17:34:14.338] bind node usb_phy@2620738
[17:34:14.338]    - attempt to match compatible string 'ti,keystone-usbphy'
[17:34:14.338] No match for node 'usb_phy@2620738'
[17:34:14.371] bind node usb@2680000
[17:34:14.371]    - attempt to match compatible string 'ti,keystone-dwc3'
[17:34:14.371] No match for node 'usb@2680000'
[17:34:14.371] bind node wdt@022f0080
[17:34:14.371]    - attempt to match compatible string 'ti,keystone-wdt'
[17:34:14.371]    - attempt to match compatible string 'ti,davinci-wdt'
[17:34:14.371] No match for node 'wdt@022f0080'
[17:34:14.371] bind node timer@22f0000
[17:34:14.371]    - attempt to match compatible string 'ti,keystone-timer'
[17:34:14.381] No match for node 'timer@22f0000'
[17:34:14.381] bind node gpio@260bf00
[17:34:14.381]    - attempt to match compatible string 'ti,keystone-gpio'
[17:34:14.381] No match for node 'gpio@260bf00'
[17:34:14.397] bind node aemif@21000A00
[17:34:14.397]    - attempt to match compatible string 'ti,keystone-aemif'
[17:34:14.397]    - attempt to match compatible string 'ti,davinci-aemif'
[17:34:14.397] No match for node 'aemif@21000A00'
[17:34:14.414] bind node keystone_irq@26202a0
[17:34:14.414]    - attempt to match compatible string 'ti,keystone-irq'
[17:34:14.414] No match for node 'keystone_irq@26202a0'
[17:34:14.414]    - ignoring disabled device
[17:34:14.414] bind node keystone_dsp_gpio@02620240
[17:34:14.429]    - attempt to match compatible string 'ti,keystone-dsp-gpio'
[17:34:14.429] No match for node 'keystone_dsp_gpio@02620240'
[17:34:14.429] bind node keystone_dsp_gpio@2620244
[17:34:14.429]    - attempt to match compatible string 'ti,keystone-dsp-gpio'
[17:34:14.445] No match for node 'keystone_dsp_gpio@2620244'
[17:34:14.445] bind node keystone_dsp_gpio@2620248
[17:34:14.445]    - attempt to match compatible string 'ti,keystone-dsp-gpio'
[17:34:14.461] No match for node 'keystone_dsp_gpio@2620248'
[17:34:14.461] bind node keystone_dsp_gpio@262024c
[17:34:14.461]    - attempt to match compatible string 'ti,keystone-dsp-gpio'
[17:34:14.461] No match for node 'keystone_dsp_gpio@262024c'
[17:34:14.477] bind node keystone_dsp_gpio@2620250
[17:34:14.477]    - attempt to match compatible string 'ti,keystone-dsp-gpio'
[17:34:14.477] No match for node 'keystone_dsp_gpio@2620250'
[17:34:14.477] bind node keystone_dsp_gpio@2620254
[17:34:14.493]    - attempt to match compatible string 'ti,keystone-dsp-gpio'
[17:34:14.493] No match for node 'keystone_dsp_gpio@2620254'
[17:34:14.493] bind node keystone_dsp_gpio@2620258
[17:34:14.493]    - attempt to match compatible string 'ti,keystone-dsp-gpio'
[17:34:14.509] No match for node 'keystone_dsp_gpio@2620258'
[17:34:14.509] bind node keystone_dsp_gpio@262025c
[17:34:14.509]    - attempt to match compatible string 'ti,keystone-dsp-gpio'
[17:34:14.525] No match for node 'keystone_dsp_gpio@262025c'
[17:34:14.525]    - ignoring disabled device
[17:34:14.525] bind node rapidio@2900000
[17:34:14.525]    - attempt to match compatible string 'ti,keystone-rapidio'
[17:34:14.541]    - found match at 'rio_keystone'
[17:34:14.541] Bound device rapidio@2900000 to soc
[17:34:14.541] bind node qmss@2a40000
[17:34:14.541]    - attempt to match compatible string 'ti,keystone-navigator-qmss'
[17:34:14.541] No match for node 'qmss@2a40000'
[17:34:14.557] bind node knav_dmas@0
[17:34:14.557]    - attempt to match compatible string 'ti,keystone-navigator-dma'
[17:34:14.557] No match for node 'knav_dmas@0'
[17:34:14.557] bind node netcp@2000000
[17:34:14.573]    - attempt to match compatible string 'ti,netcp-1.0'
[17:34:14.573]    - found match at 'eth_ks2'
[17:34:14.573] Looking for 'eth' at 26120, name netcp@2000000
[17:34:14.573]    - serial0, /soc/serial@02530c00
[17:34:14.573]    - spi0, /soc/spi@21000400
[17:34:14.589]    - spi1, /soc/spi@21000600
[17:34:14.589]    - spi2, /soc/spi@21000800
[17:34:14.589] Not found
[17:34:14.589] Bound device netcp@2000000 to soc
[17:34:14.589] Bound device soc to root_driver
[17:34:14.589] bind node cpus
[17:34:14.605] Device 'cpus' has no compatible string
[17:34:14.605] bind node leds
[17:34:14.605]    - attempt to match compatible string 'gpio-leds'
[17:34:14.605] No match for node 'leds'
[17:34:14.621] initcall: 0c00e17f (relocated to bff3217f)
[17:34:14.621] initcall: 0c002351 (relocated to bff26351)
[17:34:14.621] initcall: 0c03dabd (relocated to bff61abd)
[17:34:14.621] efi_add_memory_map: 0x80000000 0x40000 7 no
[17:34:14.637] efi_add_memory_map: 0x0 0x0 7 no
[17:34:14.637] efi_add_memory_map: 0xbcedb000 0x3125 2 no
[17:34:14.637] efi_add_memory_map: 0xbff8e000 0x1 5 no
[17:34:14.637] initcall: 0c014f35 (relocated to bff38f35)
[17:34:14.637] initcall: 0c00e175 (relocated to bff32175)
[17:34:14.653] uclass_find_device_by_seq: 0 -1
[17:34:14.653] uclass_find_device_by_seq: 0 0
[17:34:14.653]    - -1 -1
[17:34:14.653]    - not found
[17:34:14.653] uclass_find_device_by_seq: 0 0
[17:34:14.669]    - 0 -1
[17:34:14.669]    - -1 -1
[17:34:14.669]    - not found
[17:34:14.669] OF: ** translation for device serial@02530c00 **
[17:34:14.669] OF: bus is default (na=1, ns=1) on soc
[17:34:14.685] OF: translating address: 000c5302
[17:34:14.685] OF: parent bus is default (na=1, ns=1) on 
[17:34:14.685] OF: no ranges, 1:1 translation
[17:34:14.701] OF: parent translation for: 00000000
[17:34:14.701] OF: with offset: 38996992
[17:34:14.701] OF: one level translation: 000c5302
[17:34:14.701] OF: reached root node
[17:34:14.701] fdtdec_get_int: reg-offset: (not found)
[17:34:14.701] fdtdec_get_int: reg-shift: 0x2 (2)
[17:34:14.717] fdtdec_get_int: clock-frequency: (not found)
[17:34:14.717] initcall: 0c00e161 (relocated to bff32161)
[17:34:14.717] Now running in RAM - U-Boot at: bff24000
[17:34:14.717] initcall: 0c00e0b9 (relocated to bff320b9)
[17:34:14.733] initcall: 0c00e14d (relocated to bff3214d)
[17:34:14.733] NAND:  512 MiB
[17:34:14.733] initcall: 0c00e105 (relocated to bff32105)
[17:34:14.733] fdtdec_get_config_int: load-environment
[17:34:14.733] *** Warning - bad CRC, using default environment
[17:34:15.134] 
[17:34:15.134] Destroy Hash Table: bff8771c table = 00000000
[17:34:15.150] Create Hash Table: N=508
[17:34:15.150] DELETE CANDIDATE: "bootargs"
[17:34:15.150] hdelete: DELETE key "bootargs"
[17:34:15.150] DELETE ERROR ##############################
[17:34:15.150] INSERT: table bff8771c, filled 1/509 rv bdf2d628 ==> name="bootcmd" value="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern"
[17:34:15.182] INSERT: table bff8771c, filled 2/509 rv bdf2ee38 ==> name="bootdelay" value="2"
[17:34:15.182] INSERT: table bff8771c, filled 3/509 rv bdf2dd80 ==> name="baudrate" value="115200"
[17:34:15.198] INSERT: table bff8771c, filled 4/509 rv bdf2de5c ==> name="arch" value="arm"
[17:34:15.198] INSERT: table bff8771c, filled 5/509 rv bdf2e6e0 ==> name="cpu" value="armv7"
[17:34:15.214] INSERT: table bff8771c, filled 6/509 rv bdf2e460 ==> name="board" value="ks2_evm"
[17:34:15.214] INSERT: table bff8771c, filled 7/509 rv bdf2e26c ==> name="board_name" value="ks2_evm"
[17:34:15.230] INSERT: table bff8771c, filled 8/509 rv bdf2cc8c ==> name="vendor" value="ti"
[17:34:15.230] INSERT: table bff8771c, filled 9/509 rv bdf2e4c4 ==> name="soc" value="keystone"
[17:34:15.246] INSERT: table bff8771c, filled 10/509 rv bdf2ebf4 ==> name="loadaddr" value="0x82000000"
[17:34:15.262] INSERT: table bff8771c, filled 11/509 rv bdf2d90c ==> name="kernel_addr_r" value="0x82000000"
[17:34:15.262] INSERT: table bff8771c, filled 12/509 rv bdf2dfc4 ==> name="fdtaddr" value="0x88000000"
[17:34:15.278] INSERT: table bff8771c, filled 13/509 rv bdf2ea78 ==> name="fdt_addr_r" value="0x88000000"
[17:34:15.278] INSERT: table bff8771c, filled 14/509 rv bdf2d178 ==> name="rdaddr" value="0x88080000"
[17:34:15.294] INSERT: table bff8771c, filled 15/509 rv bdf2d060 ==> name="ramdisk_addr_r" value="0x88080000"
[17:34:15.294] INSERT: table bff8771c, filled 16/509 rv bdf2df88 ==> name="scriptaddr" value="0x80000000"
[17:34:15.310] INSERT: table bff8771c, filled 17/509 rv bdf2e474 ==> name="pxefile_addr_r" value="0x80100000"
[17:34:15.326] INSERT: table bff8771c, filled 18/509 rv bdf2d7e0 ==> name="bootm_size" value="0x10000000"
[17:34:15.326] INSERT: table bff8771c, filled 19/509 rv bdf2dce0 ==> name="boot_fdt" value="try"
[17:34:15.342] INSERT: table bff8771c, filled 20/509 rv bdf2d68c ==> name="name_fw_rd" value="k2-fw-initrd.cpio.gz"
[17:34:15.342] INSERT: table bff8771c, filled 21/509 rv bdf2cfd4 ==> name="set_rd_spec" value="setenv rd_spec ${rdaddr}:${filesize}"
[17:34:15.358] INSERT: table bff8771c, filled 22/509 rv bdf2da4c ==> name="init_fw_rd_net" value="dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; run set_rd_spec"
[17:34:15.374] INSERT: table bff8771c, filled 23/509 rv bdf2f2ac ==> name="init_fw_rd_nfs" value="nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; run set_rd_spec"
[17:34:15.390] INSERT: table bff8771c, filled 24/509 rv bdf2e348 ==> name="init_fw_rd_ramfs" value="setenv rd_spec -"
[17:34:15.390] INSERT: table bff8771c, filled 25/509 rv bdf2d3e4 ==> name="init_fw_rd_ubi" value="ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; run set_rd_spec"
[17:34:15.406] INSERT: table bff8771c, filled 26/509 rv bdf2f298 ==> name="boot" value="ubi"
[17:34:15.422] INSERT: table bff8771c, filled 27/509 rv bdf2eac8 ==> name="args_ubi" value="setenv bootargs ${bootargs} rootfstype=ubifs root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048"
[17:34:15.438] INSERT: table bff8771c, filled 28/509 rv bdf2d7b8 ==> name="name_fdt" value="keystone-k2hk-evm.dtb"
[17:34:15.438] INSERT: table bff8771c, filled 29/509 rv bdf2e3e8 ==> name="name_mon" value="skern-k2hk.bin"
[17:34:15.454] INSERT: table bff8771c, filled 30/509 rv bdf2d8d0 ==> name="name_ubi" value="k2hk-evm-ubifs.ubi"
[17:34:15.470] INSERT: table bff8771c, filled 31/509 rv bdf2e258 ==> name="name_uboot" value="u-boot-spi-k2hk-evm.gph"
[17:34:15.470] INSERT: table bff8771c, filled 32/509 rv bdf2e35c ==> name="name_fs" value="arago-console-image-k2hk-evm.cpio.gz"
[17:34:15.486] INSERT: table bff8771c, filled 33/509 rv bdf2e2a8 ==> name="bootdir" value="/boot"
[17:34:15.502] INSERT: table bff8771c, filled 34/509 rv bdf2d6b4 ==> name="tftp_root" value="/"
[17:34:15.502] INSERT: table bff8771c, filled 35/509 rv bdf2e410 ==> name="nfs_root" value="/export"
[17:34:15.518] INSERT: table bff8771c, filled 36/509 rv bdf2da60 ==> name="mem_lpae" value="1"
[17:34:15.518] INSERT: table bff8771c, filled 37/509 rv bdf2eaf0 ==> name="addr_ubi" value="0x82000000"
[17:34:15.534] INSERT: table bff8771c, filled 38/509 rv bdf2dbb4 ==> name="addr_secdb_key" value="0xc000000"
[17:34:15.534] INSERT: table bff8771c, filled 39/509 rv bdf2e294 ==> name="name_kern" value="zImage"
[17:34:15.550] INSERT: table bff8771c, filled 40/509 rv bdf2ea14 ==> name="addr_mon" value="0x87000000"
[17:34:15.550] INSERT: table bff8771c, filled 41/509 rv bdf2ece4 ==> name="addr_non_sec_mon" value="0x0c087fc0"
[17:34:15.566] INSERT: table bff8771c, filled 42/509 rv bdf2cc28 ==> name="addr_load_sec_bm" value="0x0c08c000"
[17:34:15.582] INSERT: table bff8771c, filled 43/509 rv bdf2cb60 ==> name="run_mon" value="mon_install ${addr_mon}"
[17:34:15.582] INSERT: table bff8771c, filled 44/509 rv bdf2d164 ==> name="run_mon_hs" value="mon_install ${addr_non_sec_mon} ${addr_load_sec_bm}"
[17:34:15.598] INSERT: table bff8771c, filled 45/509 rv bdf2d984 ==> name="run_kern" value="bootz ${loadaddr} ${rd_spec} ${fdtaddr}"
[17:34:15.613] INSERT: table bff8771c, filled 46/509 rv bdf2cf70 ==> name="init_net" value="run args_all args_net"
[17:34:15.613] INSERT: table bff8771c, filled 47/509 rv bdf2d074 ==> name="init_nfs" value="setenv autoload no; dhcp; run args_all args_net"
[17:34:15.630] INSERT: table bff8771c, filled 48/509 rv bdf2e884 ==> name="init_ubi" value="run args_all args_ubi; ubi part ubifs; ubifsmount ubi:rootfs;"
[17:34:15.646] INSERT: table bff8771c, filled 49/509 rv bdf2ec44 ==> name="get_fdt_net" value="dhcp ${fdtaddr} ${tftp_root}/${name_fdt}"
[17:34:15.662] INSERT: table bff8771c, filled 50/509 rv bdf2cd7c ==> name="get_fdt_nfs" value="nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}"
[17:34:15.662] INSERT: table bff8771c, filled 51/509 rv bdf2e5dc ==> name="get_fdt_ubi" value="ubifsload ${fdtaddr} ${bootdir}/${name_fdt}"
[17:34:15.678] INSERT: table bff8771c, filled 52/509 rv bdf2ed20 ==> name="get_kern_net" value="dhcp ${loadaddr} ${tftp_root}/${name_kern}"
[17:34:15.694] INSERT: table bff8771c, filled 53/509 rv bdf2d600 ==> name="get_kern_nfs" value="nfs ${loadaddr} ${nfs_root}/boot/${name_kern}"
[17:34:15.710] INSERT: table bff8771c, filled 54/509 rv bdf2db8c ==> name="get_kern_ubi" value="ubifsload ${loadaddr} ${bootdir}/${name_kern}"
[17:34:15.710] INSERT: table bff8771c, filled 55/509 rv bdf2e500 ==> name="get_mon_net" value="dhcp ${addr_mon} ${tftp_root}/${name_mon}"
[17:34:15.725] INSERT: table bff8771c, filled 56/509 rv bdf2d894 ==> name="get_mon_nfs" value="nfs ${addr_mon} ${nfs_root}/boot/${name_mon}"
[17:34:15.742] INSERT: table bff8771c, filled 57/509 rv bdf2e640 ==> name="get_mon_ubi" value="ubifsload ${addr_mon} ${bootdir}/${name_mon}"
[17:34:15.758] INSERT: table bff8771c, filled 58/509 rv bdf2e85c ==> name="get_fit_net" value="dhcp ${fit_loadaddr} ${tftp_root}/${fit_bootfile}"
[17:34:15.773] INSERT: table bff8771c, filled 59/509 rv bdf2d538 ==> name="get_fit_nfs" value="nfs ${fit_loadaddr} ${nfs_root}/boot/${fit_bootfile}"
[17:34:15.773] INSERT: table bff8771c, filled 60/509 rv bdf2e9d8 ==> name="get_fit_ubi" value="ubifsload ${fit_loadaddr} ${bootdir}/${fit_bootfile}"
[17:34:15.790] INSERT: table bff8771c, filled 61/509 rv bdf2cc64 ==> name="get_fit_mmc" value="load mmc ${bootpart} ${fit_loadaddr} ${bootdir}/${fit_bootfile}"
[17:34:15.806] INSERT: table bff8771c, filled 62/509 rv bdf2eed8 ==> name="get_uboot_net" value="dhcp ${loadaddr} ${tftp_root}/${name_uboot}"
[17:34:15.821] INSERT: table bff8771c, filled 63/509 rv bdf2cebc ==> name="get_uboot_nfs" value="nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}"
[17:34:15.837] INSERT: table bff8771c, filled 64/509 rv bdf2d038 ==> name="burn_uboot_spi" value="sf probe; sf erase 0 0x90000; sf write ${loadaddr} 0 ${filesize}"
[17:34:15.837] INSERT: table bff8771c, filled 65/509 rv bdf2ed5c ==> name="burn_uboot_nand" value="nand erase 0 0x100000; nand write ${loadaddr} 0 ${filesize}"
[17:34:15.854] INSERT: table bff8771c, filled 66/509 rv bdf2d7cc ==> name="args_all" value="setenv bootargs console=ttyS0,115200n8 rootwait=1"
[17:34:15.870] INSERT: table bff8771c, filled 67/509 rv bdf2d1b4 ==> name="args_net" value="setenv bootargs ${bootargs} rootfstype=nfs root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},${nfs_options} ip=dhcp"
[17:34:15.885] INSERT: table bff8771c, filled 68/509 rv bdf2eff0 ==> name="nfs_options" value="v3,tcp,rsize=4096,wsize=4096"
[17:34:15.902] INSERT: table bff8771c, filled 69/509 rv bdf2d678 ==> name="get_fdt_ramfs" value="dhcp ${fdtaddr} ${tftp_root}/${name_fdt}"
[17:34:15.918] INSERT: table bff8771c, filled 70/509 rv bdf2e118 ==> name="get_kern_ramfs" value="dhcp ${loadaddr} ${tftp_root}/${name_kern}"
[17:34:15.918] INSERT: table bff8771c, filled 71/509 rv bdf2d9d4 ==> name="get_mon_ramfs" value="dhcp ${addr_mon} ${tftp_root}/${name_mon}"
[17:34:15.934] INSERT: table bff8771c, filled 72/509 rv bdf2e104 ==> name="get_fit_ramfs" value="dhcp ${fit_loadaddr} ${tftp_root}/${fit_bootfile}"
[17:34:15.950] INSERT: table bff8771c, filled 73/509 rv bdf2cb10 ==> name="get_fs_ramfs" value="dhcp ${rdaddr} ${tftp_root}/${name_fs}"
[17:34:15.965] INSERT: table bff8771c, filled 74/509 rv bdf2ee24 ==> name="get_ubi_net" value="dhcp ${addr_ubi} ${tftp_root}/${name_ubi}"
[17:34:15.965] INSERT: table bff8771c, filled 75/509 rv bdf2e99c ==> name="get_ubi_nfs" value="nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}"
[17:34:15.981] INSERT: table bff8771c, filled 76/509 rv bdf2d2a4 ==> name="burn_ubi" value="nand erase.part ubifs; nand write ${addr_ubi} ubifs ${filesize}"
[17:34:15.998] INSERT: table bff8771c, filled 77/509 rv bdf2cffc ==> name="init_ramfs" value="run args_all args_ramfs get_fs_ramfs"
[17:34:16.014] INSERT: table bff8771c, filled 78/509 rv bdf2d240 ==> name="args_ramfs" value="setenv bootargs ${bootargs} rdinit=/sbin/init rw root=/dev/ram0 initrd=0x808080000,80M"
[17:34:16.030] INSERT: table bff8771c, filled 79/509 rv bdf2e4ec ==> name="no_post" value="1"
[17:34:16.030] INSERT: table bff8771c, filled 80/509 rv bdf2d588 ==> name="mtdparts" value="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
[17:34:16.045] INSERT: free(data = bdf2bd08)
[17:34:16.045] INSERT: done
[17:34:16.045] Initial value for argc=3
[17:34:16.062] Final value for argc=3
[17:34:16.062] initcall: 0c00e205 (relocated to bff32205)
[17:34:16.062] initcall: 0c014f49 (relocated to bff38f49)
[17:34:16.062] initcall: 0c00e0fb (relocated to bff320fb)
[17:34:16.129] initcall: 0c0130f9 (relocated to bff370f9)
[17:34:16.129] Initial value for argc=3
[17:34:16.129] Final value for argc=3
[17:34:16.129] Initial value for argc=3
[17:34:16.129] Final value for argc=3
[17:34:16.142] Initial value for argc=3
[17:34:16.142] Final value for argc=3
[17:34:16.142] initcall: 0c002231 (relocated to bff26231)
[17:34:16.142] initcall: 0c000c89 (relocated to bff24c89)
[17:34:16.142] initcall: 0c00e0f1 (relocated to bff320f1)
[17:34:16.157] initcall: 0c00e0d9 (relocated to bff320d9)
[17:34:16.157] initcall: 0c00e0c5 (relocated to bff320c5)
[17:34:16.157] Net:   uclass_find_device_by_seq: 0 -1
[17:34:16.157] uclass_find_device_by_seq: 0 0
[17:34:16.177]    - -1 -1
[17:34:16.177]    - not found
[17:34:16.177] fdtdec_get_int: slave-port: 0x0 (0)
[17:34:16.177] fdtdec_get_int: slave-port: 0x1 (1)
[17:34:16.177] Looking for 'eth' at 26720, name interface-1
[17:34:16.177]    - serial0, /soc/serial@02530c00
[17:34:16.189]    - spi0, /soc/spi@21000400
[17:34:16.189]    - spi1, /soc/spi@21000600
[17:34:16.189]    - spi2, /soc/spi@21000800
[17:34:16.189] Not found
[17:34:16.189] Bound device netcp@slave-1 to netcp@2000000
[17:34:16.189] fdtdec_get_int: slave-port: 0x2 (2)
[17:34:16.205] Looking for 'eth' at 26852, name port-2
[17:34:16.205]    - serial0, /soc/serial@02530c00
[17:34:16.205]    - spi0, /soc/spi@21000400
[17:34:16.205]    - spi1, /soc/spi@21000600
[17:34:16.205]    - spi2, /soc/spi@21000800
[17:34:16.205] Not found
[17:34:16.221] Bound device netcp@slave-2 to netcp@2000000
[17:34:16.221] fdtdec_get_int: slave-port: 0x3 (3)
[17:34:16.221] Looking for 'eth' at 26900, name port-3
[17:34:16.221]    - serial0, /soc/serial@02530c00
[17:34:16.221]    - spi0, /soc/spi@21000400
[17:34:16.238]    - spi1, /soc/spi@21000600
[17:34:16.238]    - spi2, /soc/spi@21000800
[17:34:16.238] Not found
[17:34:16.238] Bound device netcp@slave-3 to netcp@2000000
[17:34:16.238] fdtdec_get_int: slave-port: 0x0 (0)
[17:34:16.238] fdtdec_get_int_array_count: ti,navigator-dmas
[17:34:16.253] fdtdec_get_int: link-interface: 0x0 (0)
[17:34:16.253] fdtdec_lookup_phandle: phy-handle
[17:34:16.253] fdtdec_get_int: reg: 0x0 (0)
[17:34:16.285] fdtdec_get_addr_size_fixed: reg: addr=02090300
[17:34:16.302] OF: ** translation for device netcp@2000000 **
[17:34:16.302] OF: bus is default (na=1, ns=1) on soc
[17:34:16.317] OF: translating address: 10016202
[17:34:16.317] OF: parent bus is default (na=1, ns=1) on 
[17:34:16.334] OF: no ranges, 1:1 translation
[17:34:16.334] OF: parent translation for: 00000000
[17:34:16.334] OF: with offset: 39977232
[17:34:16.334] OF: one level translation: 10016202
[17:34:16.334] OF: reached root node
[17:34:16.334] Initial value for argc=3
[17:34:16.350] Final value for argc=3
[17:34:16.350] uclass_find_device_by_seq: 0 0
[17:34:16.350]    - -1 0
[17:34:16.350]    - found
[17:34:16.350] 
[17:34:16.350] Warning: netcp@2000000 using MAC address from ROM
[17:34:16.366] eth0: netcp@2000000uclass_find_device_by_seq: 0 -1
[17:34:16.366] uclass_find_device_by_seq: 0 0
[17:34:16.366]    - -1 0
[17:34:16.366]    - found
[17:34:16.366] uclass_find_device_by_seq: 0 1
[17:34:16.366]    - -1 0
[17:34:16.366]    - -1 -1
[17:34:16.382]    - -1 -1
[17:34:16.382]    - -1 -1
[17:34:16.382]    - not found
[17:34:16.382] fdtdec_get_int: slave-port: 0x1 (1)
[17:34:16.429] fdtdec_get_int_array_count: ti,navigator-dmas
[17:34:16.445] fdtdec_get_int: link-interface: 0x0 (0)
[17:34:16.445] fdtdec_lookup_phandle: phy-handle
[17:34:16.445] fdtdec_get_int: reg: 0x1 (1)
[17:34:16.479] fdtdec_get_addr_size_fixed: reg: addr=02090300
[17:34:16.494] fdtdec_get_addr_size_fixed: reg: addr=02620110
[17:34:16.494] 
[17:34:16.494] Warning: netcp@slave-1 (eth1) using random MAC address - b6:93:c0:cf:56:2e
[17:34:16.512] , eth1: netcp@slave-1uclass_find_device_by_seq: 0 -1
[17:34:16.512] uclass_find_device_by_seq: 0 0
[17:34:16.512]    - -1 0
[17:34:16.512]    - found
[17:34:16.512] uclass_find_device_by_seq: 0 1
[17:34:16.512]    - -1 0
[17:34:16.512]    - -1 1
[17:34:16.526]    - found
[17:34:16.526] uclass_find_device_by_seq: 0 2
[17:34:16.526]    - -1 0
[17:34:16.526]    - -1 1
[17:34:16.526]    - -1 -1
[17:34:16.526]    - -1 -1
[17:34:16.526]    - not found
[17:34:16.526] fdtdec_get_int: slave-port: 0x2 (2)
[17:34:16.589] fdtdec_get_int_array_count: ti,navigator-dmas
[17:34:16.589] fdtdec_get_int: link-interface: 0x2 (2)
[17:34:16.589] fdtdec_lookup_phandle: phy-handle
[17:34:16.589] fdtdec_get_addr_size_fixed: reg: addr=02620110
[17:34:16.606] 
[17:34:16.606] Warning: netcp@slave-2 (eth2) using random MAC address - 92:85:c8:f5:c6:cc
[17:34:16.606] , eth2: netcp@slave-2uclass_find_device_by_seq: 0 -1
[17:34:16.621] uclass_find_device_by_seq: 0 0
[17:34:16.621]    - -1 0
[17:34:16.621]    - found
[17:34:16.621] uclass_find_device_by_seq: 0 1
[17:34:16.621]    - -1 0
[17:34:16.621]    - -1 1
[17:34:16.621]    - found
[17:34:16.621] uclass_find_device_by_seq: 0 2
[17:34:16.637]    - -1 0
[17:34:16.637]    - -1 1
[17:34:16.637]    - -1 2
[17:34:16.637]    - found
[17:34:16.637] uclass_find_device_by_seq: 0 3
[17:34:16.637]    - -1 0
[17:34:16.637]    - -1 1
[17:34:16.637]    - -1 2
[17:34:16.637]    - -1 -1
[17:34:16.637]    - not found
[17:34:16.637] fdtdec_get_int: slave-port: 0x3 (3)
[17:34:16.702] fdtdec_get_int_array_count: ti,navigator-dmas
[17:34:16.702] fdtdec_get_int: link-interface: 0x2 (2)
[17:34:16.702] fdtdec_lookup_phandle: phy-handle
[17:34:16.717] fdtdec_get_addr_size_fixed: reg: addr=02620110
[17:34:16.717] 
[17:34:16.717] Warning: netcp@slave-3 (eth3) using random MAC address - 6a:4c:2e:bb:75:4a
[17:34:16.733] , eth3: netcp@slave-3
[17:34:16.733] initcall: 0c00e0bd (relocated to bff320bd)
[17:34:16.733] Initial value for argc=3
[17:34:16.733] Final value for argc=3
[17:34:16.733] fdtdec_get_config_int: bootdelay
[17:34:16.733] ### main_loop entered: bootdelay=2
[17:34:16.750] 
[17:34:16.750] fdtdec_get_config_int: kernel-offset
[17:34:16.750] fdtdec_get_config_int: rootdisk-offset
[17:34:16.766] fdtdec_get_config_string: bootcmd
[17:34:16.781] fdtdec_get_config_int: bootsecure
[17:34:16.781] ### main_loop: bootcmd="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern"
[17:34:16.798] Hit any key to stop autoboot:  2  0

Q1 The ddr3 is not recognized correctly. I use 4 K4B4G1646 chip,ddr3 should be 2GiByte.The printed information show just 1GiByte.

Should I change which parts of the u-boot code to configure DDR3A?

Q2 When I input DHCP in uboot console , console show :

[17:34:16.766] fdtdec_get_config_string: bootcmd
[17:34:16.781] fdtdec_get_config_int: bootsecure
[17:34:16.781] ### main_loop: bootcmd="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern"
[17:34:16.798] Hit any key to stop autoboot:  2  0 
[17:34:17.773] => 
[17:34:17.773] => 
[17:34:17.773] => 
[17:34:17.773] => 
[17:34:18.269] => 
[17:34:18.269] => 
[17:34:18.269] => 
[17:34:18.269] => dhcpdhcp
[17:34:34.669] Unknown command 'dhcpdhcp' - try 'help'
[17:34:34.685] => 
[17:34:34.685] Unknown command 'dhcpdhcp' - try 'help'
[17:34:34.685] => dhcp
[17:34:37.565] Initial value for argc=3
[17:34:37.565] Final value for argc=3
[17:34:37.565] Trying netcp@2000000
[17:34:37.565] 
[17:34:37.565] <NULL> Waiting for SGMII auto negotiation to complete. done
[17:34:37.581] BOOTP broadcast 1
[17:34:37.581] data abort
[17:34:37.597] pc : [<bff4be24>]	   lr : [<bff4b3ab>]
[17:34:37.597] reloc pc : [<0c027e24>]	   lr : [<0c0273ab>]
[17:34:37.597] sp : bdedb8e0  ip : 000000ff	 fp : bffed1d0
[17:34:37.597] r10: bffed1ec  r9 : bdee3ee0	 r8 : 0000000e
[17:34:37.597] r7 : 0000012c  r6 : 00000156	 r5 : bffed6c0  r4 : 00000000
[17:34:37.613] r3 : 00000001  r2 : ffffffff	 r1 : e59ff098  r0 : ea000047
[17:34:37.613] Flags: nzCv  IRQs off  FIQs off  Mode SVC_32
[17:34:37.613] Resetting CPU ...
[17:34:37.613] 
[17:34:37.613] resetting ...
[17:34:37.725]

I don't kown Why ?

please help me .

over 8 years ago

0 Yordan Kovachev over 8 years ago

TI__Guru**** 161600 points

We're looking into this.

Best Regards,
Yordan

0 Jin Tian over 8 years ago in reply to Yordan Kovachev

Intellectual 340 points

Yordan，
Looking forward to your reply.

Best Ragards,
Tian

0 Rex Chang over 8 years ago in reply to Jin Tian

TI__Guru 50170 points

Hi, Tian,

You will need to refer to the DDR datasheet to set the DDR3 configuration for different memory chip. Linux u-boot ported the PHYs and EMIF parameters from Hardware team which prepared them using DDR vendor datasheet. You may be able to refer to the K2hk gel file included in CCS package (ccsv6/ccs_base/emulation/boards/xtcievmk2x/gel) for the parameters used to configure DDR3, but I am not sure how it behaves when applied on DDR3A.

U-boot displays the DDR3 size from memory SPD which it gets through I2C. I think you need to be sure the DDR is accessible by doing a memory dump on DDR3 address space before you go further.

Rex

0 Jin Tian over 8 years ago in reply to Rex Chang

Intellectual 340 points

Hi, Rex

I modify the PHYs and EMIF parameters refering to K2 DDR3 Register Calc v1p60.xlsx. The DDR3 chip K4B4G1646 I chosen is listed in the xlsx.


DDR3 Clock Timings

	Design Value	Units
DDR3 Output Clock Frequency	800.000	MHz
DDR3 Data Rate	1600.000	MT/s
DDR3 Output Clock Period	1.250	ns
Device	K4B4G1646B (1600)
Speed Grade	1600	MT/s

Note that the DDR3 PLL on KeyStone-II devices will need to output half of the DDR3 clock frequency. The DDR3 PLL output frequency will be a quarter of the DDR3 data rate. We recommend configuring the VCO of the PLL (using PLLD and PLLM) to operate at the DDR3 data rate and then programming the OD field for a divide by 4.


SDRAM and PHY Configuration

	Register Settings Selected	Recommended Value	Corresponding Register Value (decimal)	Corresponding Register Value (hex)
DDR_TERM	RZQ/4	RZQ/4	1	1
DYN_ODT	Disable ODT	Disable	0	0
SDRAM_DRIVE	RZQ/6	RZQ/7	0	0
CAS_WRITE_LATENCY	CWL = 8		3	3
Narrow Mode	64-bit bus width		0	0
ECC Byte	Disable		0	0
CAS_LATENCY	CAS = 11		14	E
IBANK	8 bank SDRAM		3	3
EBANK	Single Rank - only use CE0		0	0
PAGESIZE	1024-word page - 10 column bits		2	2
ADDRESS_MIRRORING	Address Mirroring Off		0	0
PHY Data ZO	RZQ/6 = 40 Ohms	RZQ/6	11	B
PHY ACCC ZO	RZQ/7 = 34 Ohms	RZQ/7	13	D
PHY ODT	RZQ/4 = 60 Ohms	RZQ/4	5	5
DDR3 or DDR3L	DDR3		1	1


Refresh Configuration

	Selected Datasheet Values / Settings	Units	Corresponding Register Value (decimal)	Corresponding Register Value (hex)
INITREF_DIS	Normal Operation		0	0
SRT	Normal Temp Range		0	0
ASR	Manual Self-Refresh		0	0
PASR	Full Array		0	0
REFRESH_PERIOD - Normal	7.81	us	6250	186A
REFRESH_PERIOD - Ext. Temp	3.91	us	3125	0C35

EMIF Configuration Register Values

SDRAM Register	Address (hex)	Value (hex)
DDR_SDTIM1	21010018	166C9875
DDR_SDTIM2	2101001C	00001D4A
DDR_SDTIM3	21010020	435DFF53
DDR_SDTIM4	21010028	543F0CFF
DDR_SDCFG	21010008	6200CE62
DDR_SDRFC (normal)	21010010	00001869
DDR_SDRFC (ext temp)	21010010	00000C34
DDR_ZQCFG	210100C8	70073200


PHY Configuration Register Values

SDRAM PHY Register	Address (hex)	Value (hex)
DDR3_PGCR0	02329008	A8000E3F
DDR3_PGCR1	0232900C	0080C487
DDR3_PGCR2	0232908C	00F07A12
DDR3_PLLCR	02329018	0001C000
DDR3_MR0	02329054	00001C70
DDR3_MR1	02329058	00000004
DDR3_MR2	0232905C	00000018
DDR3_MR3	02329060	00000000
DDR3_DTPR0	02329048	9D9CBB66
DDR3_DTPR1	0232904C	32868400
DDR3_DTPR2	02329050	5002D200
DDR3_PTR0	0232901C	42C21590
DDR3_PTR1	02329020	D05612C0
DDR3_PTR2	02329024	00083DEF
DDR3_PTR3	02329028	0D861A80
DDR3_PTR4	0232902C	0C827100
DDR3_DCR	02329044	0000040B
DDR3_DTCR	02329068	710035C7
DDR3_ZQ0CR1	02329184	0001005D
DDR3_ZQ1CR1	02329194	0001005B
DDR3_ZQ2CR1	023291A4	0001005B
DDR3_DX2GCR	02329240	7C000E81
DDR3_DX3GCR	02329280	7C000E81
DDR3_DX4GCR	023292C0	7C000E81
DDR3_DX5GCR	02329300	7C000E81
DDR3_DX6GCR	02329340	7C000E81
DDR3_DX7GCR	02329380	7C000E81
DDR3_DX8GCR	023293C0	7C000E80

1 I am not sure how to modify SDRAM and PHY Configuration .Hope you can validate it.

2 Can you tell me some details about U-boot displays the DDR3 size from memory SPD which it gets through I2C. Can you show me some code or some file about this ?

3 How can I do memory dump?

0 Yordan Kovachev over 8 years ago in reply to Jin Tian

TI__Guru**** 161600 points

Hi,

2 Can you tell me some details about U-boot displays the DDR3 size from memory SPD which it gets through I2C. Can you show me some code or some file about this ?

For ddr3 size, see u32 ddr3_init(void) in board/ti/ks2_evm.c:
if (cpu_revision() > 0) {
if (cpu_revision() > 1) {
/* PG 2.0 */
/* Reset DDR3A PHY after PLL enabled */
ddr3_reset_ddrphy();
spd_cb.phy_cfg.zq0cr1 |= 0x10000;
spd_cb.phy_cfg.zq1cr1 |= 0x10000;
spd_cb.phy_cfg.zq2cr1 |= 0x10000;
}
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);

ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);

ddr3_size = spd_cb.ddr_size_gbyte;
} else {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
spd_cb.emif_cfg.sdcfg |= 0x1000;
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
ddr3_size = spd_cb.ddr_size_gbyte / 2;
}

For ddr_size_gbyte you can take a look at:
arch/arm/mach-keystone/ddr3_spd.c: spd_cb->ddr_size_gbyte = ddr3_get_size_in_mb(buf) / 1024;

3 How can I do memory dump?

You can use the memory display command:
=> md
md - memory display

Usage:
md [.b, .w, .l] address [# of objects]
=>

Best Regards,
Yordan

0 Jin Tian over 8 years ago in reply to Yordan Kovachev

Intellectual 340 points

Hi Yordan,

Thank you for your quick reply.

1、In the ddr3_k2hk.c I attached above,I print the ddr3_size and the u-boot console shows 'DRAM: 2 GiB (includes reported below)'.I think it's right.

But the u-boot console will print''

[21:22:02.820] Monitor len: 000CBE98
[21:22:02.820] Ram size: 40000000
[21:22:02.820] Ram top: C0000000
[21:22:02.820] initcall: 0c00dc8d
[21:22:02.820] initcall: 0c00dd99
[21:22:02.820] TLB table from bfff0000 to bfff4000
[21:22:02.820] initcall: 0c00df25
[21:22:02.820] initcall: 0c00dd59
[21:22:02.836] Reserving 815k for U-Boot at: bff24000
[21:22:02.836] initcall: 0c00dd35
[21:22:02.836] Reserving 33024k for malloc() at: bdee4000
[21:22:02.836] initcall: 0c00dee5
[21:22:02.836] Reserving 88 Bytes for Board Info at: bdee3fa8
[21:22:02.836] initcall: 0c00df29
[21:22:02.852] initcall: 0c00dd0d
[21:22:02.852] Reserving 200 Bytes for Global Data at: bdee3ee0
[21:22:02.852] initcall: 0c00dcbd
[21:22:02.852] Reserving 33344 Bytes for FDT at: bdedbca0
[21:22:02.852] initcall: 0c00df1d
[21:22:02.852] initcall: 0c00e085
[21:22:02.868] initcall: 0c00e001
[21:22:02.868] TJ added:Bank #0 start: 80000000 TJ added:Bank #0 size: 40000000 initcall: 0c00df35
[21:22:02.868] 
[21:22:02.868] RAM Configuration:
[21:22:02.868] Bank #0: 80000000 1 GiB
[21:22:02.868] Bank #1: 0 0 Bytes
[21:22:02.868] 
[21:22:02.868] DRAM: 1 GiB

It shows just 1GiB. I donot kown Why. This is the evm board with two rank, and I only use a rank related?

2、I use 'mw and md ' in u-boot console

2.1 First, I input mw 0x80000000 0xff 0x100 ,then input md 0x80000000 0x100

u-boot shows 0x80000000-0x800003F0 is 0x000000ff, I think it's ok.

2.2 I input md 0xC0000000 0x100,u-boot console shows 0xC0000000-0xC00003F0 is 0x000000ff

then I input mw 0xC0000000 0xAB 0x100 ,then input md 0x80000000 0x100

u-boot shows 0x80000000-0x800003F0 is 0x000000AB ，it is wrong.

It looks 0x80000000 and 0xC0000000 point to the address is the same.

Best Regards,

Tian

0 Rex Chang over 8 years ago in reply to Jin Tian

TI__Guru 50170 points

Hi, Tian,

You really need to check the datasheet. I did a quick browse of the part you are using. If I am not mistaking, it is 8 bank 4GB D-Die memory chip. You will need to check if D-Die is double rank from datasheet. if it is double rank and you configure it as a single rank and 2GB, you will only get 1GB. You debug output shows bank 1 is 0 bytes which pretty much gave the answer.

Rex

0 Jin Tian over 8 years ago in reply to Rex Chang

Intellectual 340 points

Hi,Rex

You are right,The DDR3 chip I am using is 8 bank 4Gb D-Die memory chip.

But I don't understand what you said ' if D-Die is double rank'.I think 4 X16 DDR3 chip can only form single Rank.so I set

	EBANK	Single Rank - only use CE0	　	0	0

in ks2 ddr3 Register calc.xlxs.

is it right?

Best Regards,

Tian

0 Rex Chang over 8 years ago in reply to Jin Tian

TI__Guru 50170 points

Hi, Tian,

You need to check how many chip select to the DDR3 memory on your board.

Rex

0 Jin Tian over 8 years ago in reply to Rex Chang

Intellectual 340 points

Hi,Rex

I use one CS in my board.
The K4B4G1646D-BCK0 I am using just have one CS pin,so I use one CS .You can see it in page8 and page9 of my attached schematic above.
ddr3 chip in schematic is Micron_MT41J128M16JT.But I use K4B4G1646D-BCK0 actually.

Best Regards,
Tian

0 Rex Chang over 8 years ago in reply to Jin Tian

TI__Guru 50170 points

Hi, Tian,

The configuration looks good to me, but you may need to modify u-boot code for the number of banks in addition to ddr3 configuration change if you have not changed the code yet. To me the u-boot display still shows 2 banks with the 2nd bank size being 0. That seems to show the u-boot code still thinks it is dual rank and that could be reason why it only shows half of the capacity.

Rex

0 Rex Chang over 6 years ago in reply to Rex Chang

TI__Guru 50170 points

When developing on a custom board, we recommend following the Custom Board Porting Guide (linked below) in the Processor Software Development Kit (PSDK) which highlights the key considerations of creating a custom board library.

http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#custom-board-addition

PSDK contains module initialization and register configuration for the DDR memory on the TI evaluation platform. If developing on a custom board with a different external memory, please refer to the “Useful DDR configuration resources” section (linked below) in the PSDK documentation which links to various useful application notes and tools for DDR configuration on different processors.

http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/FAQ.html#useful-ddr-configuration-resources

Specifically for Keystone-II family of devices, we recommend referring to the Keystone II DDR3 Initialization Application Note . This app note provides a step-by-step initialization guide, a spreadsheet tool that helps compute the values for the on-chip DDR3 controller, and links to other relevant DDR3 collateral.

For Linux users, Processor SDK U-Boot code reads DDR3 SPD info to initialize DDR3 by calling ddr3_init_ddrphy() and ddr3_init_ddremif(). Based on the SPD info, init_ddr3param() sets the PHY and EMIF register values accordingly, and passes them to ddr3_init_ddrphy() and ddr3_init_ddremif(). If SPD info isn’t available, the DDR3 vendor should have PHY and EMIF configuration info and the values can be computed from the spreadsheet mentioned in Keystone II DDR3 Initialization application note. The PHY and EMIF configuration parameters should replace those set in init_ddr3param().

For Keystone-II devices, this can be done by defining the structures of PHY and EMIF registers as in boot/board/ti/ks2_evm/ddr3_cfg.c. The PHY and EMIF configuration structures are used to configure DDR3 as the sample code below:

ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);

ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);

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66AK2H14: How to modify DDR configuration in u-boot code?