AM3352: Pixel clock question

xuanbao tu

Part Number: AM3352

HI Dear,

I'm choosing AM3552 Sitara™ Processors for my project, and I use a 10.4" TFT-LCD panel I'm choosing the lcd_clk=600MHz,so lcd_pclk=40MHz(lcd_pclk=lcd_clk/clkdiv),but the table above (specification in attach file).show the max of lcd_clk is 200MHz,it is ture when I choose the lcd_clk=600MHz?or I must choose below the 200MHz about the lcd_clk from display pll_clkout? why?

Thank you in advance.

TuXB

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Hi,

LCD_CLK is the input functional clock to the LCD controller and 200MHz is the maximum frequency for this clock. This is divided by the value stored in the "clkdiv" bitfield of the LCD controller CTRL register to provide the actual pixel clock. Possible frequencies are LCD_CLK /2 through LCD_CLK /255.

0 xuanbao tu over 8 years ago in reply to Biser Gatchev-XID

Prodigy 100 points

Thank you for your answer.
TXB

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AM3352: Pixel clock question