Hello.
I would like to make sure the AM437X DDR controller .
From below url, I am understanding AM437X DDR controller assume AL = 0 in any cases. Is my understanding correct?
Biser Gatchev-XID said:Ivan FrederiksMicron defines ODTLon as CWL + AL - 2. Is this equation standard for all DDR3 parts?
It means MR1 reg. AL field should be set to 0 from DDR3 memory point of view.
Best regards, RY