How is the PLLM register set in DM648 sd_loopback example?

Eddie3909

I can't figure out how this is done? The CLKIN1 is 33 MHz yet the tcf file says

/* BIOS Timer Fix - This can be removed later */
bios.GBL.CLKOUT = 891.0000;
bios.CLK.SPECIFYRATE = 1;
bios.CLK.INPUTCLK = 148.5000;

Where does the 148.5 come from? Shouldn't this be set to 33? Or maybe this has nothing to do with the PLLM setup? The BIOS must be setting PLLM for PLL1 up somewhere but I can't figure out where.

How is the PLLM for PLL2 setup by the BIOS? (DDR clock)

The sd_loopback example is in:

C:\dvsdk_1_10_00_26_DM648\pspdrivers_1_10_00_09\packages\ti\sdo\pspdrivers\system\dm648\bios\evmDM648\video\sample\build

One other question. The example defines the struct below. Where is it used?

Thx

/* I2C Default Initial Parameters */
PSP_I2cConfig I2C_devParams =
{
    /** Driver operation mode                       */
    PSP_OPMODE_INTERRUPT,
    /**< Own address (7 or 10 bit)                  */
    I2C_OWN_ADDR,
    /**< Number of bits/byte to be sent/received    */
    I2C_NUM_BITS,
    /**< I2C Bus Frequency                          */
    I2C_BUS_FREQ,
    /**< Module input clock freq                    */
    I2C_INPUT_BUS_FREQ,
    /**< 7bit/10bit Addressing mode                 */
    FALSE,
    /**< Digital Loob Back (DLB) mode enabled       */
    FALSE
};

over 16 years ago

0 Bernie Thompson TI over 16 years ago

TI__Mastermind 41665 points

Eddie said:
How is the PLLM for PLL2 setup by the BIOS? (DDR clock)

BIOS does not actually setup the PLLs, even though it has these frequency settings in the TCF file, rather the PLLs are generally configured by your boot loader, or while debugging with CCS by your GEL file that is defined in CCS setup for your board, so what settings you are actually using can be found in your GEL file. BIOS has these clock settings for the purposes of providing real world time values for operations within BIOS that require such timing, for example to have a periodic function that goes off every 100mS BIOS needs to know how fast the timers will be going off. If you set the frequency values wrong in BIOS it will only impact such timing related features, for example if you give it a lower value than it is actually running your PRDs will run fast, if you give it a higher value than it is actually running than your PRDs will run slow.

Eddie said:
The example defines the struct below. Where is it used?

I have not really done much work with these examples but this is probably used by the video drivers internally somewhere, since the I2C bus is what is used to configure the external video encoders/decoders.

0 Eddie3909 over 16 years ago in reply to Bernie Thompson TI

Guru 10385 points

I see now, the 148.5 comes from the 891/6 for SYSCLK3 (Timer clocks)

Thanks Bernie

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How is the PLLM register set in DM648 sd_loopback example?