Hi Team!
My customer is using the AM3352 processor in a network time server application.
They are seeing a lot of jitter on the ethernet RGMII transmit clock out of the AM3352 processor. The processor has a 25MHz reference clock. When they look at the 125MHz RGMII clock vs the 25 MHz reference clock, there is so much jitter they can barely tell that the two clocks are phase coherent at all. This is the same for the DDR3 clock, so I think the jitter is coming from the interal PLLs. Is this expected?
Do you have any information about the jitter performance of the clock PLLs inside the AM3352? How much jitter should they expect to see? Is there anything that can be done to improve the jitter performance?
Best Regards,
Peter
