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DRA712: How to change CPU freq from 1Ghz to 600Mhz

Raul Matos
Expert 5125 points
Part Number: DRA712
Other Parts Discussed in Thread: DRA718,

Team,

my customer needs to scaled down maximum CPU frequency from 1Ghz to 600Mhz. This is needed for performance test of DRA712 on a DRA718 EVM.

Is there any CPUFreq function available on the latest Android SDK? If not, what's the best way to change it?

Regards,

Raul matos

  • 0
    TI__Intellectual 1285 points
    Hi Raul,

    The question is forwarded to an expert.

    Best regards
    Lucy
  • 0 in reply to Lyudmila Kamenova
    TI__Mastermind 33090 points
    Hi Raul,

    Could you try below change to Kernel and check if it takes effect?


    diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
    index a05300c..70eaf84 100644
    --- a/arch/arm/boot/dts/dra7.dtsi
    +++ b/arch/arm/boot/dts/dra7.dtsi
    @@ -102,8 +102,8 @@
    compatible = "operating-points-v2";
    opp-shared;

    - opp_nom@1000000000 {
    - opp-hz = /bits/ 64 <1000000000>;
    + opp_nom@600000000 {
    + opp-hz = /bits/ 64 <600000000>;
    opp-microvolt = <1060000 850000 1150000>;
    opp-supported-hw = <0xFF 0x01>;
    opp-suspend;


    Regards,
    Vishal
  • 0 in reply to Vishal Mahaveer
    TI__Expert 5125 points
    Customer will try this and provide an answer asap.
    BTW one thing we noted on the Ti Android 6AM.1.3 release is that despite the EVM having the CPU governor enabled in the Kernel the CPU is always at 1Ghz even in user-idle. Is this supposed to be right?
  • 0 in reply to Raul Matos
    TI__Mastermind 33090 points
    Hi Raul,

    In a part with only one OPP, in this case only 1 GHz, there is no OPP to switch to for the governor.
    For CPUFreq governor to work you need multiple OPPs (Like J6, J6 Eco)
  • 0 in reply to Vishal Mahaveer
    TI__Expert 5125 points

     

    Vishal, going back to the original topic. The EVM won't start with the setting you provided. The kernel performs a restart as seen below.

     

    [    3.602827] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm

    [    3.609049] cpu0 supply vdd not found, using dummy regulator

    [    3.615113] cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 1000000 KHz

    [    3.622648] cpu cpu0: dev_pm_opp_domain_set_rate: failed to find current OPP for freq 1000000000 (-34)

    [    3.632098] ti_oppdm 4a003b20.oppdm: vdd failed for voltage 925000uV(ref=1060000uV)[min 850000uV max 1500000uV]:-22

    [    3.642641] cpufreq: __target_index: Failed to change cpu frequency: -22

    [    3.649383] ------------[ cut here ]------------

    [    3.654018] Kernel BUG at c08be52c [verbose debug info unavailable]

    [    3.660310] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM

    [    3.666167] Modules linked in:

    [    3.669243] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.45 #1

    [    3.675186] Hardware name: Generic DRA72X (Flattened Device Tree)

    [    3.681303] task: ee8d8000 ti: ee8e0000 task.ti: ee8e0000

    [    3.686731] PC is at cpufreq_online+0x710/0x730

    [    3.691282] LR is at __wake_up+0x4c/0x54

    [    3.695222] pc : [<c08be52c>]    lr : [<c027b7a8>]    psr: a0000013

    [    3.695222] sp : ee8e19e0  ip : ee8e1938  fp : ee8e1a24

    [    3.706748] r10: c1404638  r9 : c128e5c8  r8 : c1523f34

    [    3.711993] r7 : c1523f34  r6 : 00000000  r5 : 00000000  r4 : ee392900

    [    3.718546] r3 : dc8ba62d  r2 : dc8ba62d  r1 : 80000013  r0 : ffffffea

    [    3.725100] Flags: NzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel

    [    3.732438] Control: 30c5387d  Table: 80003000  DAC: fffffffd

    [    3.738207] 

    [    3.738207] PC: 0xc08be4ac:

    [    3.742492] e4ac  e34c010e e3a0a001 eb0cebe0 eafffeca e30f07b4 e59f1080 e5942010 e34c010e

    [    3.750775] e4cc  e594302c eb0cebd9 e594102c e1a00004 e3a02000 e2411001 ebfff69a e3500000

    Can you check the settings you provided?

    Regards, 

    Raul Matos

  • 0 in reply to Raul Matos
    TI__Mastermind 33090 points
    Hi Raul,

    You need an update to u-boot as well for 600 MHz operation.
    Below change along with Kernel change mentioned before should get you to 600 MHz.

    diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
    index 2fab367..c3aa622 100644
    --- a/arch/arm/cpu/armv7/omap5/hw_data.c
    +++ b/arch/arm/cpu/armv7/omap5/hw_data.c
    @@ -42,7 +42,7 @@ static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
    /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
    static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
    {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
    - {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
    + {300, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
    {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
    {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
    {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

    Regards,
    Vishal
  • 0 in reply to Vishal Mahaveer
    TI__Expert 5125 points
    Vishal, thank you. This implementation has worked in order to limit DRA712 to 600Mhz.

    Is it possible to limit RAM capability from DDR1333 to DDR1066 through Software?

    Regards,
    Raul Matos
  • 0 in reply to Raul Matos
    TI__Mastermind 33090 points
    It's possible.
    I can point you to an old example where we tried some experiments
    review.omapzoom.org/