Hello All,
I am trying to debug an IRQ (Timer0) on the eZdsp 'C5515 board (TMX Silicon).
When using the simple demo. program, I am able to set a breakpoint in the TimerIRQ and all is well. I have noticed the TConf part of DSP/BIOS is part of that build. I have removed all DSP/BIOS references in the build I am developing.
I am finding that setting a breakpoint in the Timer0 IRQ difficult, I am seeing IER0 being cleared - I set Bit 4 to enable Timer0 and it is getting cleared. I have looked in the CPU v.3.3 manual to see what can clear IER0, but there doesn't seem to be much info on that. I am also wondering if clearing global maskable interrupts (INTM) and then reenabling without also writing back to IER0 could be an issue here - in other words, is there an order you have to follow when enabling and disabling IRQ's - maybe so since I am disabling IRQ's and re-enabling in my code.
Also, I tried setting up DBIER0 in my code (Bit 4), and that doesn't seem to have much of a difference. Sometimes when I have the debugger halted and I see that IER0 bit 4 and DBIER0 bit 4 is cleared, I set those manually and then the debugger will jump to my Timer0 IRQ breakpoint. But it doesn't always happen.
So, I guess my questions are this in summary:
*) Did disabling the TConf part in the build of DSP/BIOS have anything to do with this - I don't think so, but that is a difference in the build that works vs. the one that doesn't. Also, in the default build (eZdsp_Sample..?) DBIER0 isn't set and it seems to go to the IRQ without issue.
*) Is there an order that has to be followed to enable interrupts? There is a reference to this in the CPU v.3.3 manual (sec. 2.8.3, p. 2.28, and also note (2) on page 5-3 is food for thought...), but I am not sure if global IRQ's are disabled, should an order be followed, and what is the order? Note I am running the RTC IRQ in this code as well, and there doesn't seem to be the same issue with the RTC IRQ as the Timer0 IRQ - but RTC is set in IER1 - not sure if that has anything to do with the issue.
*) Does DBIER0 Bit 4 have to be set in able to debug the Timer0 IRQ? From the example, the answer seems to be no, but when you read the CPU manual v.3.3 (Sec. 2.8.4) - the answer seems to be yes. And, the RTC IRQ seems to be just fine on both builds. Perhaps DBIER0 Bit 4 only has to be enabled if you are single-stepping and want to step into the IRQ while the debugger is halted. That implies to me that DBIER0 Bit 4 should only be set in the debugger, or is it OK to set in your code too?
Thanks In Advance,
John W.
