Linux/AM5728: DDR3 IO control

Hi Yordan,

Thank you for quick reply.
I understand that it is not set up with u-boot.

Is there a problem with the following parts of the source to be added?
If that is wrong, please tell me the detailed source location to add.

\u-boot\arch\arm\mach-omap2\emif-common.c

static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
{

-->add their registers setting

if (warm_reset()) {
emif_reset_phy(base);
writel(0x0, &emif->emif_pwr_mgmt_ctrl);
}
do_ext_phy_settings(base, regs);

....

}

Best Regards,
Shigehiro Tsuda

Hi Yordan,

Thank you for quick reply.

I confirmed the source of u-boot again,
It seems that it is set with io_settings_ddr 3 () of the following source.

arch\arm\mach-omap2\omap5\hwinit.c

The value I think is that it is used in the setting is below.

arch\arm\mach-omap2\omap5\hw_data.c

const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x80808080,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x04A52000,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};

Is the definition used in AM572x correct in DRA752_ES2_0?

Best Regrds,
Shigehiro Tsuda