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tms320c6657: Power on reset status of PLLCTL register

David Johnson30
Prodigy 140 points
Part Number: TMS320C6657

The Data sheet (SPRS814C.) for the C665x 1/2 core DSP processors does not provide information regarding the electrical state of PLLCTL register at power on reset.  The operation of this register is detailed in the Keystone PLL (SPRUGV2H) guide, however this guide defers to the product data sheet to specify the "-n" power-on reset state of all PLL controller registers.

I'm  interested in knowing the power up configuration of the core clocking per diagram on page 82 of the C665x data sheet  SPRS814C.

My specific question:

   What is reset value for  C6657's  PLLCTL register @ MM address = 0x0231 0100?    Again the Keystone PLL document refers one to the product data sheet.   But this is in fact omitted from the data sheet.  

  • 0
    TI__Guru 65405 points
    Hi David,

    I've forwarded this to the hardware design experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 140 points

    I encountered section 6.29  "PLL Boot Configuration Settings"   pg 191 of C665x data sheet.   

    Table 6-100 implies PLL core clocking at boot time is controlled by BOOTMODE[12:10] pin-straps.

        1)  Does this apply for a boot mode = "No Boot" as well ?   (BOOTMODE [5:0] = 0)

    Sec 6.28.3 on page 180 refers to Boot parameter table, where Bytes [11:8] contain PLL config.  

       2)  Will this be populated with values from Table 6-100 on page 191?   (ie. Strictly contingent on the pin logic for BOOTMOD[12:10]?

  • 0
    TI__Mastermind 46460 points

    David,

    Much of the PLLCTL functionality is implemented in the MAINPLLCTL0 and MAINPLLCTL1 registers shown in the data manual in section 8.5.3.  Also note that almost all boot modes program the Main PLL during ROM BOOT execution.  Therefore, the reset status of the PLLCTL bits is not significant with the exception of the BYPASS bit.  At reset release in NOBOOT mode, all PLLs are left in BYPASS.

    Tom

  • 0 in reply to David Johnson30
    TI__Mastermind 46460 points

    David,

    I cannot find the items that you reference by page, section or table.  Exactly what datasheet are you using (i.e. document number and revision)?

    The PLL is only programmed in certain modes.  The PLL is not programmed NOBOOT mode.  Note that if you have a GEL file loaded, it may program the PLLs when you connect with CCS.

    When using the Boot Parameter Table, the values in this structure are copied to their respective destinations.

    You are asking very atomic questions.  All of this is abstracted in the supplies software routines so that you do not need to be concerned at this level.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 140 points

    Thanks for the quick response!

    I need to be sure I fully understand.  There are several bits (PLLEN, PLLENSRC) in a register designated as MMR  PLLCTL (as per the Keystone 1 PLL guide).  As far as I can tell, there is nowhere in the PLL Guide or 665x data sheet that explicitly states the "out-of-reset" state of these bits, yet they have the capability of routing the CORECLK P|N around the PLL, directly to the entire SYSCLK divider chain of the SoC.

    Your statement is that,  in the No Boot case  (BOOTCONFIG [5:0] = 000000b), the PLL is not engaged.  And the CORECLK P|N bypasses the PLL to drive each SYSCLKn divider.   As such, the BOOTCONFIG[12:10] bits have no effect as per table 6-100 of the data sheet in the "No Boot" case where the ROM B/L is not executing (and this boot param table would be ignored).

    Please confirm...

    Background:

      My project has developed an environmental "test sled" on which we have mounted a C6657.  Very little is wired up from the 6657-, just grounds to a plane, and CVDD's to a plane. 

    But all balls are brought to bottom side pads.  I'm looking to attach a minimal amount of wires from an external "start up" circuit that has sequencing logic, supplies & load switches, resets, LVDS clocks for Core & DDR and JTAG) to determine if 6657 is (to extent that can be assessed) in good functional condition.  Wish to keep clocking frequencies low as possible (Core & DDR need to be >= 40 MHz). 

    ( I do have a number of the EVMs.  I assume I could set one up for "no Boot" arrangement, and with a minimal GEL script, determine the out-of-reset state of the 6657 from CC debugger.  But it is helpful to have full clarity about what the design is intended to do... the 6657 EVM is a complex circuit.)