The Data sheet (SPRS814C.) for the C665x 1/2 core DSP processors does not provide information regarding the electrical state of PLLCTL register at power on reset. The operation of this register is detailed in the Keystone PLL (SPRUGV2H) guide, however this guide defers to the product data sheet to specify the "-n" power-on reset state of all PLL controller registers.
I'm interested in knowing the power up configuration of the core clocking per diagram on page 82 of the C665x data sheet SPRS814C.
My specific question:
What is reset value for C6657's PLLCTL register @ MM address = 0x0231 0100? Again the Keystone PLL document refers one to the product data sheet. But this is in fact omitted from the data sheet.