• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 97 subscribers
  • Views 1303 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3357: DDR2 timing requirements

Hiroshi Takakura
Prodigy 40 points

Part Number: AM3357

Dear sirs,

For design verification as to the timing of DDR2 interface, I need information about DDR2-EMIF of AM335x.

Are there the specification information?
 ("se" represents single ended signal, and "diff" represents diffirential signal)


1)  Input of seDQsignal and diffDQS
 I'm planning to measure the timing as to the seDQ signal at AM3357, to verify that the seDQ meets the requirement of input stage of AM3357.

 1-1) seDQ input setup/hold time from diffDQS.
 1-2) seDQ input setup/hold time from diffCK (if required).
 1-3) diffDQS input setup/hold time from diffCK (if required).


2) AM3357 Output specifications
 To set the margin due to disparison of AM3357 for timing at DDR2-SDRAM.

 2-1) diffDQS output access time from diffCK.
 2-2) seDQ output access time from diffDQS.
 2-3) seAddress/Command output access time from diffCK.

Best regards,

Hiroshi Takakura

  • 0
    TI__Guru**** 393215 points
    Hi,

    All available information is given in the AM335x Datasheet Rev. J, section 7.7.2.2. For EMIF configuration this wiki should be followed: processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips

    There is no other information available.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 40 points

    Hi,


    Thank you for your reply.
    And I'm sorry, I reply too late.

    I know the information that you provided. However, I wanted to verify with actual measured value (timing).


     I have other question.

    According to the Table 7-55 of the datasheet, there's no requirement for skew matching between data bytes (DQS0 and DQ0" and "DQS1 and DQ1" net classes).
    And also, there's no mention about skew matching between CK and DQSs.

    As a result, in some cases, there are big skew mismatching among "CK and ADDR_CTRL", "DQS0 and DQ0" and "DQS1 and DQ1" net classes.

    I know that there are several registers for compensating the skew mismatching between "CK and ADDR_CTRL" and "DQSx and DQx" net classes. For example, DATAx_PHY_RD DQS_SLAVE_RATIO etc..
    But,"Ratio Seed Spreadsheet.xlsx" calcurates averaged compensation value for Byte0 and Byte1.

    And "DDR PHY Registers for DDR2 and LPDDR (mDDR)" clause of wiki says
     "For CMDx, x is 0, 1, 2 as described above. For DATAx, x is 0 or 1 as described above. In all cases, program the same value for each iteration of the macro."
    So, if there's large skew mismatching between "DQS0 and DQ0" and "DQS1 and DQ1" net classes, the compensation might not be enough for each net classes.

    So, I think that there might be some requirement for skew mismatching between "DQS0 and DQ0" and "DQS1 and DQ1" net classes. Is there some information or opinion?


    Best reards,

  • 0 in reply to Hiroshi Takakura
    TI__Genius 9655 points
    Hiroshi-san

    We don't provide any timing information on the DDR interface. Please read the DDR layout section of the AM335x data sheet regarding this. As you mentioned, there are layout requirements for making sure the DDR timings are met.

    For DDR3, there is no requirement for DQS0, DQS1 and CK length matching. The SW leveling procedure compensates for this length mis-match. We found out that AM335x using average length meets the performance requirements due to the following reasons:
    - 16-bit interface
    - max. routing length constraints the lengths
    - max. frequency is 400MHz i.e. tDQSCK of 1.25ns (+/-625ps)

    Let me know if you still have any other questions

    Regards, Siva