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CCS/TMS320C6678: C6678 hyperlink error

YUCHAO WANG
Expert 1265 points
Part Number: TMS320C6678

Tool/software: Code Composer Studio

Hi TI engineer

In our application, we want to accomplish a kind of process to check the hyperlink
between two C6678s. The way to check it is like this: C6678-A send data to C6678-B, then send a intr
through hyplnk; C6678-B answers this intr, send data back to c6678-A, then send a intr back through
hyplnk.The process will continue for some cycles.

But during the test, we found that sometimes the process will be blocked. During this
happens, it is like this:

1. C6678-A didn't get the last data and intr from C6678-B;

2. In c6678-b, the value of regs 0x2140004c is 0x00000002. In commen sense it should be
0x00000000.So it seems like there is a 2-bit error, isn't it?

Could you give us some advice on how this happens?Thank you very much.Looking forward for your
reply.

Regards,

Yuchao

  • 0
    TI__Guru 65405 points
    Hi Yuchao,

    I've forwarded this to the hyperlink experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    Expert 1265 points
    Hi XID
    there is more information about this.
    During the problem happens, the value of hyperlink register is as following:
    DSP B
    reg Addr wrong value right value
    0x21400008 0x04400105 0x04400005
    0x2140000c 0x0000000d 0x80000000
    0x21400010 0x00002000 0x00000000
    0x21400014 0x00002000 0x00000000
    0x2140004c 0x00000001 0x00000000
    DSP A
    hyperlink register is unAvailable to access. When try to read it in memory browser, the core is in hang then.
  • 0 in reply to YUCHAO WANG
    TI__Guru* 95265 points
    Hi,

    Please discribe your HW setup, TI EVM ----cable----TI EVM? Also, what is the SW package you used? And it works sometime, correct?

    Please provide 0x2140_0058 in both working and failure case. It looks to me, there is 2-bit ECC error in the system (seen from 0x2140_004c) and link is down. So when you read through the Hyperlink, the core is hang. You need have an error free connection between two SOCs, also try to run it at lower speed (e.g 3.125Gb/s x 4 lanes) at first.

    Regards, Eric
  • 0 in reply to lding
    Expert 1265 points
    Hi Eric
    I have solved this problem. It seems this error is coming from the register Lane Power Management Control Register (Base Address + 0x44). If we set quadlane singlelane zerolane all to 1, then it will happen. If we only set quadlane to 1,then the problem doesn't occur any more.
    Could you give us some advice on this?
    Thank you very much.
  • 0 in reply to YUCHAO WANG
    TI__Guru* 95265 points
    Hi,

    I knew there is some instability issue when you enables zero lane, single lane at the Hyperlink initialization time. It is good to always use quad-lane only.

    Regards, Eric