Part Number: TCI6638K2K
Hi,
My customer has some questions about Lane-to-Lane Rx skew on PCIe 5.0GT/s.
We read KeyStone II Architecture Serializer/Deserializer User's Guide (SPRUHO3A.pdf).
"10.1 Relevant Industry Standard Specification Support" said
"The PCIe interface on KeyStone II devices is compliant with Physical Layer Specifications referenced in Chapter 4 of the PCI Express Base Specification Revision 2.0."
So we checked the spec and found LRX-SKEW is max 8ns (= 8000ps).
But "10.2 Recommended SerDes PCB Layout Constraints" said
"All complementary PCIe receive pairs PCIERXN/P1:0 shall be assigned to an individual net class where routing skew shall not be greater than 100 ps between all receive pairs. (The full link budget is 2UI+500ps so lane to lane skew can be larger if additional system analysis is completed.)".
1) The 100ps on User's guide is very tighter value than 8ns on PCI Spec 2.0. Could you please tell us the condition how to measure it?
2) We couldn't find the value "2UI+500ps" in LRX-SKEW of PCIe spec 2.0. We found "2UI+500ps" in LTX-SKEW and 2.5GT/s. Could you please tell us how to get the value "2UI+500ps"? Is this the simulation result?
Best Regards,
M.Ohhashi
